In May 2007, John Cooley released the results of his "2007 verification census". He has conducted the poll from 818 engineers and he concluded that "SystemVerilog" use is up, "e" use is down and that most engineers think verification languages such as "e" and "Vera" will be dead in 5 years.
People who were using Verilog in 2005 was reduced from 59% to nearly 55% in 2007. It says most of the military companies in USA uses VHDL with the rest of the world using verilog.
Among the simulators used in the current industry, Synopsys VCS topped number 1 with 44% followed by Mentor's modelsim.
Courtesy : http://www.deepchip.com/posts/dvcon07.html
People who were using Verilog in 2005 was reduced from 59% to nearly 55% in 2007. It says most of the military companies in USA uses VHDL with the rest of the world using verilog.
Among the simulators used in the current industry, Synopsys VCS topped number 1 with 44% followed by Mentor's modelsim.
Courtesy : http://www.deepchip.com/posts/dvcon07.html
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