Clock Skew

In circuit design, clock skew is a phenomenon in synchronous circuit in which the clock signal arrives at different components at different times. This can be caused by many different things, such as wire-interconnect length, temperature variations and differences in input capacitance on the clock inputs of devices using the clock It is a fundamental design principle that timing must satisfy register setup and hold time requirements. Both data propagation delay and clock skew are parts of these calculations.

The problem of short data path is very similar to hold-time violations when there is a skew. The problem will come when the data propagation delay is less than the clock skew. Figure shows an example to illustrate a short data path problem.
When the clock travels more slowly than the path from one register to another - allowing data to penetrate two registers in the same clock tick, which results in a functional error.

The delay blocks in a sample circuit is shown in Figure.
The delays in Figure are as follows:

1. tCQ1: The clock to output delay of the first FF.
   
2. tRDQ1: The propagation delay from the first flip-flop to the input of the second FF.
3. tCK2: The clock skew.

The short-path problem will occur when

tCK2 > tCQ1 + tRDQ1 -tHOLD2

Where tHOLD2 is the hold-time requirement of the sink flip-flop.

Minimizing the Clock Skew:

The short data path problem is created by the clock skew. Therefore, minimizing the clock skew is the best method to reduce the short-path problems.

Add Delay in Data Path:

Increasing the tRDQ1 (routing delay in the data path) to a value greater than the clock skew will eliminate the short path problem.

To insert delay in the data path, the engineers can employ BUFD macros as a delay elements.

Figure shows a simple example of BUFD insertion in the data path.
The amount of the inserted delay in the data path should be large enough so that the data path delay is greater than the clock skew.

Clock Reversing:

Clock reversing is another method to get around the problem of short data paths and clock skew. In this method, the clock signal arrives at the receiving FF earlier than the source FF. Therefore, the receiving FF will clock in the transmitting FF's value before the transmitting FF receives its clock edge.

Conclusion:

The difference in the arrival times of the clock signals between two FFs may cause the design to malfunction when the data paths are short. The simplest method to prevent the short data path problem is to minimize the clock skew.