Increase the operational speed of the circuit

There are numerous design techniques exists to increase the speed of the digital circuit. These design techniques are implemented automatically during synthesis. It also involves the trade-off between the area and speed, means that you have to pay for more area in order to achieve a speed.

1. Use And-Or-Invert or Or-And-Invert gates wherever possible, since they are economical particularly for both area and speed.
2. Feed the late arriving signals in your design late into the combinatorial circuit to balance the total gate delay along each path of the combinatorial circuit. To know more about late arriving signals, please go thorough it here.
   
3. Use a maximum of 2 inputs on all combinatorial circuits in your design. For example, you can use two numbers of 2 input NAND gates and a 2 input NOR gate instead of using a 4 input AND gate.
4. The bottom line is, if a boolean function with more than 2 inputs are decomposed into several simple gates, which results in more gates for the same function; but the total delay is reduced. According to the gate delay model, an N-input AND gate contains a branch with N transistors in series, resulting in an increased internal resistance of N*delta. Furthermore, the parasitic capacitance is also increased; therefore the internal delay of an N input AND gate is N(square)*delta. So if the NAND gate with 6 inputs is not decomposed, the internal delay will be rougly 0.7 ns as opposed to 0.42 ns with decomposition.
5. Use Johnson counters instead of binary counters.
   
6. An n-stage johnson counter produces a set of outputs of length 2n, which can be decoded to give a count sequence. The advantage of using this counter is that, having no combinatorial logic between flip-flops, it can be run at the maximum speed permitted by setup and hold time constraints. The disadvantage of a johnson counter is that, for a required count of m, it requires m/2 flip-flops, rather than log2(m) as required by a synchronous binary counter.

Gray Code Counter Implementation

A Gray code is an encoding of numbers so that adjacent numbers have a single digit differing by 1. The term Gray code is often used to refer to a Binary Reflected Gray Code. We can implement a gray code counter in a different ways. Consider the following table carefully.

B : 000, 001, 010, 011, 100, 101, 110, 111
G: 000, 001, 011, 010, 110, 111, 101, 100

To convert a binary number d1,d2,..,d(n-1),dn to its corresponding Binary Reflected Gray Code, start at the right with the digit dn (the LSB). If the d(n-1) is 1, replace dn by (1-dn); otherwise, leave it unchanged. Then proceed to d(n-1). Continue up to the first d1, which is kept the same. The resulting number g1,g2,..,g(n-1),gn is the Reflected Binary Gray Code.

The most common Gray code is where the lower half of the sequence is exactly the mirror image of first half with only the MSB inverted. We illustrate the 3-bit binary Gray code as an example.

Binary to gray code can be achieved by

gray[2] = binary[2];

gray[1] = binary[2] ^ binary[1];

gray[0] = binary[1] ^ binary[0];

A simple verilog code to implement this function is given by

assign gray = (binary>> 1) ^ binary; // Right shift by 1 and EX-OR with binary.

 module gray_cntr (  
     clock_in,
     rst_n,
     enable_in,
     cnt_out
    );
    
    // I/O Declarations

    input clock_in, rst_n, enable_in; 
    output [ 2:0] cnt_out;
    wire [2:0] cnt_out;
    reg [2:0] cnt;
    
    always @ (posedge clock_in or negedge rst_n) 
    if (!rst_n) 
      cnt <= 1'b0; 
    else if (enable_in) 
      cnt <= cnt + 1'b1; 
      
    assign cnt_out = { cnt[2], (^cnt[2:1]), (^cnt[1:0]) };
      
  endmodule

Serial to Parallel Data Conversion

A serial to parallel data conversion requires n-bit shift register. Therefore, a serial-in/parallel-out shift register converts data from serial format to parallel format. If four data bits are shifted in by four clock pulses via a single wire at serial-in, the data becomes available simultaneously on the four outputs parallel_out[3] to parallel_out[0] after the fourth clock pulse.

A serial to parallel data conversion circuit is used for converting a serial word supplied by some domain "X" to a parallel word so as to allow for the processing of the parallel word by a processor. The "X" domain supplies to the interface circuit a 'ready' pulse signal. The interface circuit, in response to the 'ready' pulse signal, supplies an 'ack' pulse and a 'clock' signal to the "X", so as to allow the serial word from the "X" to be transferred to the interface circuit, which then converts the serial word to a parallel word. An enable pulse signal supplied to the interface circuit effects the transfer of the parallel word from the interface circuit to the processor.

module serial_2_parallel (
clk_in,
rst_n,
ready_in,
shift_enable,
serial_in,
ack_out,
parallel_out );

// I/O declarations

input clk_in;
input rst_n;
input ready_in;
input shift_enable;
input serial_in;

output [3:0] parallel_out;
reg [3:0] parallel_out;
output ack_out;
reg ack_out;

wire [3:0] parallel_wire;

// A 4-bit shift register to convert serial to parallel

always@(posedge clk_in or negedge rst_n)
begin
if(rst_n == 1'b0)
begin
parallel_out <= 4'b0;
ack_out <= 1'b0; // ack_out is initially 0
end
// Shift enable is driven from tb as 1 when ack_out is 1
else if (shift_enable == 1'b1 && ready_in == 1'b1)
parallel_out <= ({serial_in, parallel_wire[3:1]});
else
begin
parallel_out <= parallel_wire;
ack_out <= 1'b1;
end
end

// Declare a 4-bit wire

assign parallel_wire = parallel_out;

endmodule

Fact about Johnson counter

The Johnson counter is made of a simple shift register with an inverted feedback. That is if the complement output of a ring counter is fed back to the input instead of the true output, a Johnson counter results. Figure shows the 4-bit Johnson counter with 2*4=8 states.

Johnson counter have 2n states where "n" is the number of flip-flops. But normal binary counters have (2 power n) states for the same number of flops. Here the interesting news about the Johnson counter is unused states. The formula used to find out the unused states is (2 power n) - (2n). Here, in this case, the number of unused states are (2 power 4) - (2*4) = 8 states.

Parity Detector

N number of EX-NOR gates is connected in series such that the N inputs (A0, A1, A2......) are given in the following way:

A0 and A1 is being given to first EX-NOR gate and A2 and output of first EX-NOR is being given to second EX-NOR gate and so on. Nth EX-NOR gate's output is final output. How does this circuit work? Explain in detail?

Solution:

If N= Odd ( # of EX-NOR gates are Odd), the circuit acts as even parity detector, i.e. the output will 1 if there are even number of 1's in the inputs. This could also be called as odd parity generator since with this additional 1 as output the total number of 1's will be Odd.

If N= Even ( # of EX-NOR gates are Even), the circuit acts as odd parity detector, i.e. the output will 1 if there are odd number of 1's in the inputs. This could also be called as even parity generator since with this additional 1 as output the total number of 1's will be Even.

Clock Dividers

Dividing a clock by an even number always generates 50% duty cycle output. Sometimes it is necessary to generate a 50% duty cycle frequency even when the input clock is divided by an odd or non-integer number. In this post I am going to talk about how to divide a clock by an odd number.

The easiest way to create an odd divider with a 50% duty cycle is to generate two clocks at half the desired output frequency with a quadrature-phase relationship (constant 90° phase difference between the two clocks). You can then generate the output frequency by exclusive-ORing the two waveforms together. Because of the constant 90° phase offset, only one transition occurs at a time on the input of the exclusive-OR gate, effectively eliminating any glitches on the output waveform.

Let’s see how it works by taking an example where the REF_CLK is divided by 3.

• Create a counter which is incremented on every rising edge of the input clock (REF_CLK) and the counter is reset to ZERO when the terminal count of counter reaches to (N-1). where N is odd number (3, 5, 7 and so on)
  

• Take two toggle flip-flops and generate their enables as follows; T-FF1 is enabled when the counter reaches '0' and T-FF2 is enabled when the counter reaches (N/2)+1.
  

• Output of T-FF1 is triggered on rising edge of REF_CLK and output of T-FF2 is triggered on the falling edge of REF_CLK.
  

• The divide by N clock is derived by simply Ex-ORing both the output of T-FFs.
  

The above Figure shows the timing diagram for the above steps.

Sequence Detector - Solution

The solution for the problem is given here.

Sequence Detector

Design a state machine, that outputs a '1' one and only when two of the last 3 inputs are '1'. For example, if the input sequence is 0110_1110 then the output will be 0011_1101. Assume that the input 'x' is a single bit serial line.

Mod - 10 counter

A Mod-10 counter has 10 possible states, in other words it counts from 0 to 9 and rolls over. Let's take a look at how to build a Mod-10 counter.

The first step is to determine how many flip-flops to use. We will use JK FFs for our design. Since we need 10 states, 4 FFs will be required. The trick is to find a way not to use all of those states. There must be a way to force the counter to stop counting at 9 and roll over to 0. This is where an asynchronous inputs come into play. The asynchronous inputs can over-ride the synchronous inputs and force the outputs to either LOW or HIGH.

Looking at the truth table, the counter should run from 0000 to 1001 and roll over to 0000 again. Since the counter has to display 1001, the next binary value 1010 will be used to reset the counter to 0. For a JK FF, we have an asynchronous input called CLEAR, when you assert this, flop's output goes to 0. Since this CLEAR input is active high, we can use AND gate. The 2 FFs where a '1' occurs will be tied to an AND gate and the output will be tied to a CLEAR input. When the counter goes to 1001, the AND gate has a value '1' on its output and will activate the CLEAR inputs of all FFs.

DAG

Suppose we wanted to add an OAI gate, OAI(A, B,C) = not [(A + B) ⋅C], to the target gate library for our synthesizer. If the synthesizer uses the Directed Acyclic Graph (DAG) covering method for mapping equations to gates, what would be the appropriate primitive DAG (i.e., an equivalent circuit which uses only inverters and 2-input NANDs) for this new gate?

Counter design using FSM

Design a 3-bit counter that counts in binary or in Gray code, depending on the values of a “mode control input”. This synchronous 3-bit counter has a mode control input m. As long as m = 0, the counter steps through the binary sequence 000, 001, 010, 011, 100, 101, 110, 111 and repeats this sequence. As long as m = 1, the counter advances through the Gray code sequence 000, 001, 011, 010, 110, 111, 101, 100 and repeats this sequence. However, it is possible that the mode input changes at any time in any of these sequences.

For example, assume that the mode input is 0 for the first two clock cycles but changes to 1 in the third clock cycle and stays at 1 in the fourth clock cycle. (That is, m goes through the sequence 0, 0, 1, 1.) Then, the output will be 000, 001, 010, 110, 111. In this example, 000 is the initial state. The first two state transitions (000->001->010) occurs in the binary counting mode. Then, because m = 1 from the third clock cycle onwards, the state goes from 010->110->->111, as indicated in the Gray code sequence.

In addition to the mode control input, there is a reset input. This synchronous counter should go to the 000 state if asserted.

FSM Problem

Construct a synchronous moore state machine with two inputs, A and B, and two outputs, X and Y. The machine accepts data on two input lines synchronously with the clock. The output X is 1 if and only if the data on the two input lines have been identical (i.e. A and B are both 1, or A and B are both 0) for the last three or more consecutive clock cycles. Output Y is 1 if and only if the data on the two input lines have been complements of each other (i.e. A = 1 and B = 0, or A = 0 and B = 1) for the last three or more consecutive clock cycles.

State Diagram

Draw the state diagram and state table for the circuit which produces the output '1' when the aggregate serial binary input is divisible by 5.

Design a FF

An CS flip-flop, where C and S are inputs, has the following behavior:

• If C = 1, the next state is the complement of the current state
• If C = 0, the next state of the flip-flop is equal to S

Show how to implement an CS flip-flop using a JK flip-flop and logic gates such as NOT, AND, and OR.

Digital Logic Families

Digital logic families are classified according to the technologies they are built with. Following are the families of digital logic.

• DL : Diode Logic.
• RTL : Resistor Transistor Logic.
• DTL : Diode Transistor Logic.
• TTL : Transistor Transistor Logic.
• I2L : Integrated Injection Logic.
• ECL : Emitter coupled logic.
• MOS : Metal Oxide Semiconductor Logic (PMOS and NMOS).
• CMOS : Complementary Metal Oxide Semiconductor Logic.

Among these, only CMOS is most widely used by the ASIC designers; We need to understand a few basic concepts. If you become a ASIC designer, you may need to know these concepts very well.

The most desirable features, a designer would want in IC applications are as follows.

• Fast switching speed
• Low power dissipation
• Wide noise margins
• High fan-out capability
• High packing density and
• Low cost

Although no single family has all these features, some may come close.

Switching Speed

The switching speed of the device is the measured output response to an input change. Typically, a given logic circuit will have many inputs and outputs, with various input to output path and each with a different path delay. Furthermore, switching speed is differ for both low-high and high-low, but both of which are measured from 50% point of the input signal to the 50% point of the output response. Typically tplh > tphl. The maximum value of propagation delay is one of the interest to designers, since it is used to determine useful factors. For the modern CMOS devices, this value lie b/w 0.1 ns to 10 ns.

Power Dissipation

Logic devices consumes power when they operate and this power is dissipated in the form of heat. CMOS power consumption is frequency dependent. Since each gate is connected to the power supply (Vdd). The gate draws certain amount of current during its operation.

• ICCH - Current drawn during high state
• ICCL - Current drawn during low state
• ICCT - Current drawn during transition state

For CMOS, ICCH and ICCL current is negligible, in comparison to ICCT. So the Average power dissipation is calculated as below.

Average Power Dissipation = Vdd * ICCT

So, for CMOS families, the power dissipation depends on the operating frequency. The useful figure of merit for logic devices is called the "Power delay product" and is the multiplication of power consumption and the average tp.

PDP = power_consumption * tp(avg)

Since it is desirable for a given logic device to have a both low power consumption and a small propagation delay (fast switching speed), a low PDP is desirable. Power dissipation is proportional to the heat generated by the chip; Excessive heat dissipation may increase operating temperature and cause gate circuitry to drift out of its normal operating range; It will cause gates to generate improper output values. Thus, power dissipation of any gate implementation must be kept as low as possible. CMOS circuits dissipate power by charging and discharging the various load capacitances (mostly gate and wire capacitance, but also drain and some source capacitances) whenever they are switched. The charge moved is the capacitance multiplied by the voltage change. Multiply by the switching frequency to get the current used, and multiply by voltage again to get the characteristic switching power dissipated by a CMOS device: P = CV²f.

Noise Margin

Noise Margin is the difference between what the driver IC outputs as a valid logic voltage and what the receiver IC expects to see as a valid logic voltage. There are two different types of noise margin, one for a logic high value [1] and one for a logic low value [0]. The equations for noise margins are provided below.

Noise Margin Output high = V_OH [driving device] - V_IH [receiving device]
Noise Margin Output low = V_IL [receiving device] - V_OL [driving device]

The higher the numbers the better, with negative numbers indicating in-operability.

Fan In

Fan-in is the number of inputs a gate has, like a two input AND gate has fan-in of two, a three input NAND gate as a fan-in of three. So a NOT gate always has a fan-in of one. The figure below shows the effect of fan-in on the delay offered by a gate for a CMOS based gate. Normally delay increases following a quadratic function of fan-in.

Fan Out

The number of gates that each gate can drive, while providing voltage levels in the guaranteed range, is called fan-out. The fan-out depends on the amount of electric current a gate can source or sink while driving other gates. The effects of loading a logic gate output with more than its rated fan-out has the following effects.

• In the LOW state, the output voltage VOL may increase above VOLmax.
• In the HIGH state, the output voltage VOH may decrease below VOHmin.
• The operating temperature of the device may increase thereby reducing the reliability of the device and eventually causing the device failure
• Output rise and fall times may increase beyond specifications
• The propagation delay may rise above the specified value
  

Multiplexing the clock

In today's VLSI industry, we are working on multi-clock domain all the time. In that case, we are often encountered to switch the functional clocks while the chip is running. This is generally implemented by multiplexing the two different clocks with select signal is generated from the internal logic.

The two clock frequencies could be totally asynchronous to each other or they may be multiples of each other. In either case, there is a chance of generating a 'glitch' on the clock line at the time of the switch. A glitch on the clock line is hazardous to the whole system, as it could be interpreted as a capture clock edge by some registers while missed by others.

But designing glitch free clock multiplexing is a tricky one. Some designers take it on the safer side by disabling both clocks, change the select signal and enable the clocks.

In this article, two different methods of designing a glitch free clock multiplexing are presented. The first method is used when clocks are multiples of each other, while the second method deals with clocks which are totally unrelated to each other.

Arrange the 4 n-bit numbers

There is a component called "X" with 2 inputs - A and B, and 2 outputs - X and Y. If you pass 2 n-bit numbers to the component X, the component produced the biggest number at the output X and the smallest number at the output Y.

Using minimum numbers of these components "X", Design a component "M" with 4 inputs A, B, C and D and 4 outputs W, X, Y and Z in which

'W' is the max (A, B, C, D), 'Z' is the min(A, B, C, D). 'X' is bigger than 'Y' but smaller than 'W' and 'Y' is bigger than 'Z' and smaller than 'X'.

Equation for ppm

Given an Ideal Frequency (f) and its uncertainty is given as plus or minus delta-f. Find the accuracy in parts per million (ppm) using f and delta-f.