STA FAQ

Here are some of the FAQs related to Static Timing Analysis. Please refer my previous topic for more information about STA.

What is STA?

STA stands for Static Timing Analysis, which is used to check whether the design meets the timing requirements across all the timing arcs.

What do you mean by Timing arcs?
Setup Timing Check, Hold Timing Check and Clock-gating Check.

How do you perform checks for asynchronous circuits?
Recovery check and removal checks are the two checks that are performed to check the asynchronous circuit. Recovery time is the minimum length of time an asynchronous control signal must be stable before the next active clock edge. The recovery slack time calculation is similar to the setup slack time calculation, but it applies asynchronous control signals.

Removal time is the minimum length of time an asynchronous control signal must be stable after the active clock edge. The removal time slack calculation is similar to the hold slack calculation, but it applies asynchronous control signals.

What are the various timing-paths?
Input to Register, Register to Register, Register to Output and Input to Output.

Tell me about the path delays.
The fundamental aim of STA is to measure the delay of every path. The value for gate delays comes from the vendor library. Interconnect delays are either estimated during synthesis or extracted after P&R. The summation of all the gates propagation delay and the interconnect delays are used to calculate the path delay. Just like synthesis, the STA is best suited for synchronous design.

What is False path?
As the STA tool determines delay, it considers only the paths that actually affect the output. If the path is never activated or sensitized, it can't contribute to the delay. Any path that doesn't change or doesn't affect the operation of the circuit should also be labeled as false path.

What is Multi cycle path?
They are the paths that intentionally require more than one clock cycle to become stable. Therefore, they require special multi-cycle setup and hold time calculations. Declaring the multi-cycle path tells the tool to adjust its measurements so it doesn't incorrectly report timing violations.

RTL vs Gate level timing:
RTL code, models a logic function without regard to its implementation, whereas gate level code specifies the exact gates required. For example, consider the code for both the cases:

RTL Code: assign out = ((a&b) | !a);

Gate level code :
and (s2, a, b);
not(s1, a);
or(out, s1, s2);

Modeling delays at the gate level is straight forward. The delay of each gate is found in the tech. library. However, manually implementing HDL code with delays for each gate is time consuming. At the pre-layout state, most design methodologies use synthesis to provide a gate model with delays.

How the tool will calculate the the maximum frequency?

The tool lists the paths for each clock domain that are selected by the user. The maximum running frequency of each clock domain is calculated based on the maximum register-to-register delay of each clock domain. It picks the longest register-register path of each clock domain, adds the setup time requirement of the destination register, and considers it as the maximum clock frequency.

The user can apply constraints on the clock frequency. Based on the user's clock period requirement, the tool calculates the maximum allowed register-to-register path delay based on the following equation,

max reg-to-reg path delay = clock period requirement – setup time requirement + clock skew

Important commands in Prime time:
Prime time offers several constructs to report design statistics such as clocks, max fanout, constraint checks and timing.

Constraint Checking

• check_timing -verbose is a powerful construct in Prime time and is recommended to run on all designs to check the constraints. Prime time can report unconstrained clocks in the design, combinational timing loops, inputs or outputs that are not constrained, multiple clocks clocking the same flop or flops that do not have a clock defined on them. This aids the designer to identify incorrect or undefined constraints earlier in the cycle.

• report_constraint generates a summary of all the constraint violations including setup/hold and the amount by which the design violates the constraint. Usage and offers available in this construct are
  

report_constraint -all_violators -verbose

Timing Reports

• report_timing reports design timing information for each path group (or clock group) and offers several switches to segregate the timing results based on max delay, min delay, recovery, removal etc. The level of detail that can be viewed in the reports can also be customized. Simple syntax for this construct is

# To report timing from one clock group to another (max_delay, setup)
report_timing -from [get_clocks clk1] -to [get_clocks clk2] -delay max

Reference:

Synopsis prime time user guide.