Timing 1

Due to a miscommunication during design, you thought your circuit was supposed to have a supply voltage of 2.1 volts and a 25 ns cycle time, and you designed it to meet those specifications. Now your boss tells you, you were supposed to have a 20 ns cycle time. To avoid redesigning the whole circuit, your co-worker suggests increasing the voltage of the circuit to decrease the delay to 20 ns. The same co-worker also suggests picking some arbitrary number like 3.5 volts.

1. Determine the new cycle time of your circuit with a 3.5 volt input voltage.
2. Calculate the increase in power consumption of your circuit at 3.5 volts.
3. To satisfy your boss, calculate the minimum voltage you would increase the supply voltage to, in order to allow your circuit to run at 20 ns.
   

You may leave your answer in non-simplified numeric terms, but not in the form of an equation to solve.

STA question 1

Suppose we are building the following circuit using only three components:

• Inverter: tcd = 0.5ns, tpd = 1.0ns, tr = tf = 0.7ns
• 2-input NAND: tcd = 0.5ns, tpd = 2.0ns, tr = tf = 1.2ns
• 2-input NOR: tcd = 0.5ns, tpd = 2.0ns, tr = tf = 1.2ns

What is tpd (Propagation delay) for this circuit?
What is tcd (Contamination delay) for this circuit?
What is tpd of the fastest equivalent circuit built using only above 3 components?

Hint:
tpd - Max. cumulative propagation delay considering all path b/w input and output.
tcd - Min. cumulative contamination delay.

STA FAQ

Here are some of the FAQs related to Static Timing Analysis. Please refer my previous topic for more information about STA.

What is STA?

STA stands for Static Timing Analysis, which is used to check whether the design meets the timing requirements across all the timing arcs.

What do you mean by Timing arcs?
Setup Timing Check, Hold Timing Check and Clock-gating Check.

How do you perform checks for asynchronous circuits?
Recovery check and removal checks are the two checks that are performed to check the asynchronous circuit. Recovery time is the minimum length of time an asynchronous control signal must be stable before the next active clock edge. The recovery slack time calculation is similar to the setup slack time calculation, but it applies asynchronous control signals.

Removal time is the minimum length of time an asynchronous control signal must be stable after the active clock edge. The removal time slack calculation is similar to the hold slack calculation, but it applies asynchronous control signals.

What are the various timing-paths?
Input to Register, Register to Register, Register to Output and Input to Output.

Tell me about the path delays.
The fundamental aim of STA is to measure the delay of every path. The value for gate delays comes from the vendor library. Interconnect delays are either estimated during synthesis or extracted after P&R. The summation of all the gates propagation delay and the interconnect delays are used to calculate the path delay. Just like synthesis, the STA is best suited for synchronous design.

What is False path?
As the STA tool determines delay, it considers only the paths that actually affect the output. If the path is never activated or sensitized, it can't contribute to the delay. Any path that doesn't change or doesn't affect the operation of the circuit should also be labeled as false path.

What is Multi cycle path?
They are the paths that intentionally require more than one clock cycle to become stable. Therefore, they require special multi-cycle setup and hold time calculations. Declaring the multi-cycle path tells the tool to adjust its measurements so it doesn't incorrectly report timing violations.

RTL vs Gate level timing:
RTL code, models a logic function without regard to its implementation, whereas gate level code specifies the exact gates required. For example, consider the code for both the cases:

RTL Code: assign out = ((a&b) | !a);

Gate level code :
and (s2, a, b);
not(s1, a);
or(out, s1, s2);

Modeling delays at the gate level is straight forward. The delay of each gate is found in the tech. library. However, manually implementing HDL code with delays for each gate is time consuming. At the pre-layout state, most design methodologies use synthesis to provide a gate model with delays.

How the tool will calculate the the maximum frequency?

The tool lists the paths for each clock domain that are selected by the user. The maximum running frequency of each clock domain is calculated based on the maximum register-to-register delay of each clock domain. It picks the longest register-register path of each clock domain, adds the setup time requirement of the destination register, and considers it as the maximum clock frequency.

The user can apply constraints on the clock frequency. Based on the user's clock period requirement, the tool calculates the maximum allowed register-to-register path delay based on the following equation,

max reg-to-reg path delay = clock period requirement – setup time requirement + clock skew

Important commands in Prime time:
Prime time offers several constructs to report design statistics such as clocks, max fanout, constraint checks and timing.

Constraint Checking

• check_timing -verbose is a powerful construct in Prime time and is recommended to run on all designs to check the constraints. Prime time can report unconstrained clocks in the design, combinational timing loops, inputs or outputs that are not constrained, multiple clocks clocking the same flop or flops that do not have a clock defined on them. This aids the designer to identify incorrect or undefined constraints earlier in the cycle.

• report_constraint generates a summary of all the constraint violations including setup/hold and the amount by which the design violates the constraint. Usage and offers available in this construct are
  

report_constraint -all_violators -verbose

Timing Reports

• report_timing reports design timing information for each path group (or clock group) and offers several switches to segregate the timing results based on max delay, min delay, recovery, removal etc. The level of detail that can be viewed in the reports can also be customized. Simple syntax for this construct is

# To report timing from one clock group to another (max_delay, setup)
report_timing -from [get_clocks clk1] -to [get_clocks clk2] -delay max

Reference:

Synopsis prime time user guide.

Static Timing Analysis

What is STA?

Static Timing Analysis (STA) is a technique for estimating the delay of a digital circuit without simulation. Now a days, it is widely adopted in industry for timing verification. This topic will overview the basics of static timing analysis.

How do you ensure after the ASIC is placed and routed, that every register to register path in the design does not violate the setup and hold time? This is where STA tools comes into the picture. Those tools can fully analyze a multimillion gate ASIC in a short amount of time. The STA comes into the picture twice. Once during synthesis and again during place and route. Since Synthesis tools are third party tools, they don't give the precise delays and the delays are based on wire load models which are approximate only. Place and route tools are silicon vendor tools and hence provide better information regarding these delays.

What STA can't do?

STA can only report the paths which are violating a particular constraint. It can't make the TIMINGS MEET. STA tools can't analyze the combinational feedback loops.

The inputs to any STA tools are going to be verilog netlist, Standard Delay Format (SDF) and Standard Parasitic Extraction Format (SPEF). It also uses the standard cell and macro library to find out the cell delay, net delay & clock to Q output delay of a FF. You also need to have a Design constraint file that will tell the tool about your ASIC. The big picture of Delay modeling is shown in the following Figure.
Timing Violations:

When your STA tool analyzes your design, it is checking that each path meets the setup and hold time for the design library that you specify. Everyone of us very well know, when will setup time violation occurs. Setup violations occurs when the data path is too slow compared to the clock speed. The designer can fix the setup violations by reducing the delay in the data path. Designer can reduce the clock speed to fix the setup violation, but it is going to be a poor design technique.

Hold violations occurs when data is too fast when compared to the clock speed. If hold violations are not fixed before the chip is made, lot of problem occurs unlike setup violation where the clock speed can be reduced. To fix hold violations, designer can add more delay to the data path.

Timing Constraints:

Timing constraints are how the designer tells the STA tool about the timing behavior of the ASIC. The three minimum constraints are defining the clock, input delay, and output delay. There are four types of timing paths are available. They are :

• Input to Register (Sync),
• Register to Register (Sync),
• Register to Output (Sync) and
• Input to Output(Async). Each path has a start and endpoint

When the clocks are defined, all Register to Register paths are assumed to be constrained in one clock cycle. A path originates from either an Input port or a Register clock pin, while an end point is either an Output port or a Register data pin. All start and end point must be timing constrained.

False paths:

A false path is a path, which exists in the chip but it would never be exercised in the operation of the chip. STA tools can report violations on false paths because there is no knowledge of circuit function.

Multi-Cycle Paths:

A multi-cycle path is when a signal takes more than one clock cycle to propagate to the end point.

Calculation of path delays:

The actual path delay is the sum of net and cell delays. For a given area, average of R and C are calculated for different fanouts. Net delay is calculated by simply multiplying R with C. For example, The R value for a gate that drives 3 gates (Fanout = 3) is say 0.036, the C value for the same gate is for example 0.02, then the net delay is going to be 0.036*0.02.

Two methods for calculating path delays are lumped and pin-pin models. The main difference b/w the two models is how the paths and their delays are defined. Delays are classified either by connection or rise/fall and min/max. For more info. about these delays, readers are advised to refer verilog-HDL by palnitkar.

Report generation from STA tools:

Reporting the information stored in STA tool's database allows the user to identify timing violations and make changes to the design. PrimeTime is a famous STA tool that provides extensive commands to report setup, hold, and design rules violations.

Clock Skew

In circuit design, clock skew is a phenomenon in synchronous circuit in which the clock signal arrives at different components at different times. This can be caused by many different things, such as wire-interconnect length, temperature variations and differences in input capacitance on the clock inputs of devices using the clock It is a fundamental design principle that timing must satisfy register setup and hold time requirements. Both data propagation delay and clock skew are parts of these calculations.

The problem of short data path is very similar to hold-time violations when there is a skew. The problem will come when the data propagation delay is less than the clock skew. Figure shows an example to illustrate a short data path problem.
When the clock travels more slowly than the path from one register to another - allowing data to penetrate two registers in the same clock tick, which results in a functional error.

The delay blocks in a sample circuit is shown in Figure.
The delays in Figure are as follows:

1. tCQ1: The clock to output delay of the first FF.
   
2. tRDQ1: The propagation delay from the first flip-flop to the input of the second FF.
3. tCK2: The clock skew.

The short-path problem will occur when

tCK2 > tCQ1 + tRDQ1 -tHOLD2

Where tHOLD2 is the hold-time requirement of the sink flip-flop.

Minimizing the Clock Skew:

The short data path problem is created by the clock skew. Therefore, minimizing the clock skew is the best method to reduce the short-path problems.

Add Delay in Data Path:

Increasing the tRDQ1 (routing delay in the data path) to a value greater than the clock skew will eliminate the short path problem.

To insert delay in the data path, the engineers can employ BUFD macros as a delay elements.

Figure shows a simple example of BUFD insertion in the data path.
The amount of the inserted delay in the data path should be large enough so that the data path delay is greater than the clock skew.

Clock Reversing:

Clock reversing is another method to get around the problem of short data paths and clock skew. In this method, the clock signal arrives at the receiving FF earlier than the source FF. Therefore, the receiving FF will clock in the transmitting FF's value before the transmitting FF receives its clock edge.

Conclusion:

The difference in the arrival times of the clock signals between two FFs may cause the design to malfunction when the data paths are short. The simplest method to prevent the short data path problem is to minimize the clock skew.

Timing properties of a FF

Recently when I was browsing, I found out one article that compares the setup time and hold time of a FF to one analogy.

If the train leaves at 8:00 and you live 20 minutes away from the station, when should you leave from your house????? At 7:40.... If you leave after 7:40, you will miss the train. If you leave before 7:40, you should have enough time to get into the station. (Setup time is 20 minutes!!!).

Your friend needs help boarding the train and the train allows only 5 minutes for boarding. How long should you stay after you have arrived? 8:05 at the earliest... Without your help for the full 5 minutes, your friend is not able to board and will miss the train. (Hold time is 5 minutes!!!)

Every FF has time regions around the active clock edge in which the input should not change.

If the input changes in these restricted regions, the output may be derived from either:
the old input, the new input or even half-way in between.

I hope you all know about the setup time and hold time. Now we will see the different types of delays associated with a sequential circuit.

Maximum logic propagation delays:

Consider a synchronous circuit made of FFs with logic in between them.First FF input and output are D1 & Q1. There is some logic b/w 2 FFs and the output of logic goes to input of 2nd FF. Second FF's input and output are D2 & Q2.

The Q1 signal takes tCHQV to get out of the left FF.
The propagation delay through the gate(s) is tPD.
The D2 signal must arrive at the right FF at least tSETUP before the second clock edge.

The signal must get from the first FF to the next, in one clock cycle, thus -

tCLOCK ≥ tCHQV + tPD + tSETUP

So the gate delay, tPD, could take up the rest of the clock cycle. we can modify the above equation in the following way.

tCLOCK = tCHQV + tPD(max) + tSETUP

Minimum logic propagation delay:

One can have a valid minimum gate propagation delay. For a long hold time, one FF can flip within the long hold time and send its new output to the next FF fast enough to flip it on the same clock edge. This is when tCHQV < tHOLD.

To avoid double flips:

tHOLD ≤ tCHQV + tPD(min)


Maximum logic delays with Clock skew:

I've dedicated one topic for clock skew. Now I just define what is clock skew and the positive & negative skew.

Clock skew is when the clock edge does not reach all the FFs at the same time. Positive skew define skew as positive when the data and clock are delayed in the same direction. In most schematics the right FF will receive the delayed clock.

Positive skew increases the time available to get to the right-hand FF. If there is a positive skew in the clock, there is more time to get to the right hand FF, and tPD(MAX) is increased by the amount of the skew.

tCLOCK + tSKEW = tCHQV + tPD(MAX) + tSETUP


Minimum logic delays with Clock skew:

The minimum logic delay tPD(MIN) is made worse (increased) by positive skew. With positive clock skew, the clock to the lower flip-flop is delayed. The chance of a D1 change going through both flip-flops in one cycle increases. The tSKEW acts like an increase in the hold time of the lower flip-flop.
Clock Skew Related to Signal Delay:

Most circuits do not have a simple structure where one flip-flop is the source and another is the destination. Here we relate clock skew in circuits where the data travels in more complex paths.

Finding Minimum and Maximum Propagation Delays Given Clock Skew
• A register here is a set of edge-triggered simultaneously clocked D flip-flops.
• Registers are connected to other registers by combinational logic.
• Let the clock skew between registers be known.
• We will find the fast bound tPD(MIN) and the slow bound tPD(MAX) on the logic paths between each register pair.

The specification of FFs: tCHQV = 1 ns max; tHOLD = 0 ns min; tSETUP = 3 ns max; tSKEW A-B = +2 ns; tCLOCK = 16ns.

tPD(MIN) = tHOLD + tSKEW - tCHQV = 0 + 2 - 1 = 1 ns;
tPD(MAX) = tCLOCK + tSKEW - tSETUP - tCHQV = 16 + 2 - 3 - 1 = 14ns

For no clock skew, the propagation delay bounds are

tPD(MIN) = -1 ns (effectively 0????)
tPD(MAX) = 12ns; See the values of tPD during the presence of skew and without skew.