What is Boundary Scan?

Boundary scan is a board level design technique that provides test access to the input and output pads of ICs on PCBs. Boundary scan modifies the IO circuitry of individual ICs, so that the input and output pads of every boundary scan IC can be connected to form one or more serial boundary scan chains.

Boundary scan is used to check for shorts and opens in the interconnect between ICs on PCBs. It performs the checks by using the boundary scan chains to pass logic values b/w the pads of different ICs.

At the top level the boundary scan logic has 3 modules: the Test Access Port (TAP), the instruction and data registers.

The TAP, an external I/F between the chip and the board, consists of Test Mode Select (TMS), Test Clock (TCK), Test Data In (TDI) and Test Data Out (TDO) - that control the state of the boundary scan test logic and that provide the serial access to the instruction and data modules.

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To Maximize the Fault Coverage

The scan design technique depends on the controllability and observability of the state of DUT. Observe the following guidelines to maximize the fault coverage.

• Use Full Scan
  

• Use cells that have full functional models
  

• Fix all design rule violations, in particular
  

• Be careful when you use the gated clocks. If the clock signal at a FF is gated, a primary clock might not be able to control its state. If your design has clock gating, disable it in test mode.
  

• Generate the clocks off chip. If clock signals are generated on chip (Clock dividers), you can't control the state.
  

• Minimize the combinational feedback loops. CFL are difficult to test because they are hard to place in a known state.
  

• Use scan compatible sequential elements.
  

• Avoid uncontrollable asynchronous behavior.
  

• Control bi-directional from Primary Inputs.
  

Uncontrollable clocks and resets in Scan Insertion

When we are doing the scan insertion, we may find many uncontrollable clocks and uncontrollable asynchronous signals like set and reset violations. How to avoid these violations?

Uncontrollable clocks are coming from a combinational logic (Clock Dividers). When doing scan insertion, the control of the FF must be with respect to the TEST EN signal, ie, if TEST EN = 1, the whole chip should be in scan mode. For this all the clock of FF should be controllable at the top level.

Wherever you get a uncontrollable clock violations, please do the following :

• MUX the functional CLK with the "test clk" with the TM(Test_Mode) as the select line and then give the output of MUX as the input to the FF.

You can also use Auto-Fix to fix uncontrollable clocks and asynchronous sets and resets.

Auto-Fix can automatically fix each uncontrollable clock input as shown in Figure.


To use the Auto-fix capability:

Use the set_dft_configuration command to enable the various Auto-fix options:

To fix the uncontrollable clock, use the option -fix_clock_enable
To fix the uncontrollable asynchronous set signals, use the option -fix_set_enable
To fix the uncontrollable asynchronous reset signals, use the option -fix_reset_enable

# Enable AutoFix
set_dft_configuration -fix_clock enable \
-fix_reset enable -fix_set enable