Engineering Change Order (ECO)

I wanted to know about the ECO and how the flow will be. Recently I had a great time to work on the ECO netlist. In chip design, ECO is the process of inserting a logic change directly into the netlist after it has already been processed by an automatic tool. Before the chip masks are made, ECOs are usually done to save time, by avoiding the need for full ASIC synthesis. EDA tools are often built with incremental modes of operation to facilitate this type of ECO.

RTL bug fix


Correct your bug in RTL, run simulations for the specific scenarios to see if the problem has been fixed and it didn’t destroy any correct behavior.

Implement ECO in Synthesis netlist


Using your spare cells (Spare cells are basically elements embedded in the design which are not driving anything) and/or rewiring, implement the bug fix directly in the synthesis verilog netlist. Remember you do not re-synthesize the entire design, you are patching it locally.

Run equivalence check between synthesis and RTL

Using formal verification tool, run an equivalence check to see if the code you corrected really translates to the netlist you patched. If the two designs are equivalent you are sure that your RTL simulations would also have the same result (logically speaking) as the synthesis netlist.

Implement ECO in layout netlist

You will now have to patch your layout netlist as well. Notice that this netlist is very different than the synthesis netlist. It usually has extra buffers inserted for edge shaping or hold violation correction or maybe even totally differently logically optimized.