Will we ever get a handle on SoC verification cost?

In a presentation at International Symposium on Quality Electronic Design last week, Mentor Graphics verification and test division GM & VP Robert Hum presented an interesting good-news/bad-news scenario. On the good-news side, Hum said that after years of verification costs gobbling a larger and larger fraction of the total engineering budget for chips, and in fact after years of verification cost rising faster than revenue per design, the rate of increase in verification cost is finally starting to moderate.

http://www.edn.com/blog/1690000169/post/1710023971.html