One of the most interesting architectural decision in the design project is how to calculate the depth of a FIFO. FIFO is an intermediate logic where the data would be buffered or stored . Smaller FIFO depth can cause overflow scenario and cause a data loss.
For worst case scenario, difference in the data rate between write and read should be maximum. Hence, for write operation maximum data rate should be considered and for read operation minimum data rate should be considered for calculating the depth of the FIFO.
Any Asynchronous FIFO has a write frequency and a read frequency. Assume that the write frequency (Fw) is faster than read frequency (Fr).
Scenario 1:
Fw = 1/Tw and Fr = 1/Tr where Tw and Tr are Time periods of write and read respectively.
Scenario 2:For worst case scenario, difference in the data rate between write and read should be maximum. Hence, for write operation maximum data rate should be considered and for read operation minimum data rate should be considered for calculating the depth of the FIFO.
Any Asynchronous FIFO has a write frequency and a read frequency. Assume that the write frequency (Fw) is faster than read frequency (Fr).
Scenario 1:
Fw = 1/Tw and Fr = 1/Tr where Tw and Tr are Time periods of write and read respectively.
Consider the case of a FIFO where the 'Fw' is 100 MHz and 50 words are written into the FIFO in 100 clocks while the 'Fr' is 50 MHz and one word is read out every clock.
In the worst case scenario, the 50 words are written into the FIFO as a burst in 500 ns. In the same time duration, the read side can read only 25 words out of the FIFO. The remaining 25 words are read out of the FIFO in the 50 idle write clocks. So the depth of the FIFO should be at least 28. (Three clock cycles are for synchronizer latency).
12 comments:
synchronizer latency?
could you explain it clearly!
thanx in advance!
hi, when we use pointers in FIFO , each pointer(read & write) has to cross the domains. that means, we need synchronizer over here. the no. of flops used for this, adds the delay to the FIFO. now, depending on that delayed pointer, we need to decide the FIFO depth. this delay is called Synchronizer latency.
I am afraid this is not the worst case for calculating the FIFO depth (scenario 2). Take 200 write clock cycles. Each 100 cycles can have 50 writes (which only needs 50 write cycles). Now, in the first 100 cycles, the write side writes from 50-100 cycles, and in the second 100 cycles, it writes in 100-150 cycles, it will be 100 cycles of continuous writing from the write agent. Considering 100 cycle window, the read agent lags the write agent (at half its frequency) by 50 words. I feel the depth should be 50 and not 25. You can mail me @ gksumanth@gmail.com for more details
Thanks for sharing this link, but unfortunately it seems to be down... Does anybody have a mirror or another source? Please answer to my post if you do!
I would appreciate if a staff member here at chipverification.blogspot.com could post it.
Thanks,
Alex
Have you considered the fact that this might work another way? I am wondering if anyone else has come across something
similar in the past? Let me know your thoughts...
I agree with what Sumanth says and his calculation is correct.
Total Depth of FIFO should be 50 instead of 25.
I would have to disagree with sumanth and moorthy - having 100 writes in 100 cycles is not what the author has designed for - he says burst of 50 every 100 clocks - worst case all 50 are consecutive. If you have a requirement for 100 writes for 100 clocks then definitely the calculation will be different.
Sumanth is right.
Anonymous has a good point here... even if we put two 100 cycle blocks together, the maximum can only be 50 writes per 100 cycles. The write sequence cannot be worse than <50 writes><50 idle><50 writes><50 idle>. Two 50-cycle bursts cannot be right after each other, otherwise the spec would be for 100 writes in 100 cycles. Thus the correct FIFO depth is 25 (not including synchronizer latency).
Can you please explain how to calculate the depth of fifo when Read Freq > Write Freq.
gksumanth and moorthy
please understand that the data is coming in burst.
before getting the second packet of 50 words the whole read and write of fifo would be done and it might/might not be reset before arrival of second data packet .
even if we take your case in which for the first data packet the 50 words are written in the last 50 clock cycles of the 100 clk burst and for the second data packet 50 words are written in the first 50 clk cycle of 100 clk burst, the fifo depth calculations holds true as between these two burst of 100 clock cycles there would be a time duration in which the fifo read would be completed.
the whole concept of FIFO is built around the assumption that the data will come in burst. If the data comes as a stream (which is your case) no matter how much fifo depth you have it will always overflow or u will loose data.
it can never be <50 clk><50 writes><50 writes><50 clk>
or <50 writes><50 clk><50 writes><50 clk> or anything like that there will be a gap between the two 100 clk bursts.
<50 clk><50 writes>..........<50 writes><50 clk>
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