ASIC Verification: rise and fall time

Friday, March 28, 2008

rise and fall time

Consider the dynamic behavior of a CMOS output driving a given capacitvie load. If the resistance of the charging path is double the resistance of the discharging path, is the rise time exatly tiwce the fall time? If not, what other factors affect the transition times?

1 comment:

qa said...

there would be capacitive load and fan out too other than the one specified in query