ASIC Verification: Multiplexing the clock

Sunday, March 23, 2008

Multiplexing the clock

In today's VLSI industry, we are working on multi-clock domain all the time. In that case, we are often encountered to switch the functional clocks while the chip is running. This is generally implemented by multiplexing the two different clocks with select signal is generated from the internal logic.

The two clock frequencies could be totally asynchronous to each other or they may be multiples of each other. In either case, there is a chance of generating a 'glitch' on the clock line at the time of the switch. A glitch on the clock line is hazardous to the whole system, as it could be interpreted as a capture clock edge by some registers while missed by others.

But designing glitch free clock multiplexing is a tricky one. Some designers take it on the safer side by disabling both clocks, change the select signal and enable the clocks.

In this article, two different methods of designing a glitch free clock multiplexing are presented. The first method is used when clocks are multiples of each other, while the second method deals with clocks which are totally unrelated to each other.

1 comment:

Term paper guide said...

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