ASIC Verification: Design a FF

Friday, March 28, 2008

Design a FF

An CS flip-flop, where C and S are inputs, has the following behavior:
  • If C = 1, the next state is the complement of the current state
  • If C = 0, the next state of the flip-flop is equal to S
Show how to implement an CS flip-flop using a JK flip-flop and logic gates such as NOT, AND, and OR.

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