ASIC Verification: Clock Buffer

Sunday, March 30, 2008

Clock Buffer

I read some article about the clock buffer. Clock buffers are designed to have a equal rise and fall times. For designs with global signals, use global clock buffers to take advantage of the low-skew and high-drive strength of the dedicated global buffer tree of the target device. Your synthesis tool automatically inserts a clock buffer whenever an input signal drives a clock signal or whenever an internal clock signal reaches a certain fanout. You can instantiate the clock buffers in your design if you want to specify how the clock buffer resources should be allocated.

Some synthesis tools require you to instantiate a global buffer in your code to use the dedicated routing resource if a clock is driven from a non-dedicated I/O pin. The following Verilog examples instantiate a BUFG for an internal multiplexed clock circuit.

module clock_mux
input data_in, sel_in;
input slow_clock, fast_clock;
output data_out;

reg clock;
wire clock_gbuff;
reg data_out;

always @ (sel_in or fast_clk or slow_clk)
if (sel_in == 1'b1)
clock = fast_clk;
clock = slow_clk;

buffg gbuff_for_mux

always @ (posedge clock_gbuff)
data_out <= data_in;

There is an application note from Actel website and can be downloaded from


Anonymous said...

Hi, I wanted to know why clock buffers need to have equal rise and fall time. Please let me know.

Anonymous said...

Don't know exactly why they need to have equal rise/fall time. Probably for DDR data transfer.