ASIC Verification: Digital Logic Families

Monday, March 24, 2008

Digital Logic Families

Digital logic families are classified according to the technologies they are built with. Following are the families of digital logic.

  • DL : Diode Logic.
  • RTL : Resistor Transistor Logic.
  • DTL : Diode Transistor Logic.
  • TTL : Transistor Transistor Logic.
  • I2L : Integrated Injection Logic.
  • ECL : Emitter coupled logic.
  • MOS : Metal Oxide Semiconductor Logic (PMOS and NMOS).
  • CMOS : Complementary Metal Oxide Semiconductor Logic.
Among these, only CMOS is most widely used by the ASIC designers; We need to understand a few basic concepts. If you become a ASIC designer, you may need to know these concepts very well.

The most desirable features, a designer would want in IC applications are as follows.
  • Fast switching speed
  • Low power dissipation
  • Wide noise margins
  • High fan-out capability
  • High packing density and
  • Low cost
Although no single family has all these features, some may come close.

Switching Speed

The switching speed of the device is the measured output response to an input change. Typically, a given logic circuit will have many inputs and outputs, with various input to output path and each with a different path delay. Furthermore, switching speed is differ for both low-high and high-low, but both of which are measured from 50% point of the input signal to the 50% point of the output response. Typically tplh > tphl. The maximum value of propagation delay is one of the interest to designers, since it is used to determine useful factors. For the modern CMOS devices, this value lie b/w 0.1 ns to 10 ns.

Power Dissipation

Logic devices consumes power when they operate and this power is dissipated in the form of heat. CMOS power consumption is frequency dependent. Since each gate is connected to the power supply (Vdd). The gate draws certain amount of current during its operation.
  • ICCH - Current drawn during high state
  • ICCL - Current drawn during low state
  • ICCT - Current drawn during transition state
For CMOS, ICCH and ICCL current is negligible, in comparison to ICCT. So the Average power dissipation is calculated as below.

Average Power Dissipation = Vdd * ICCT

So, for CMOS families, the power dissipation depends on the operating frequency. The useful figure of merit for logic devices is called the "Power delay product" and is the multiplication of power consumption and the average tp.

PDP = power_consumption * tp(avg)

Since it is desirable for a given logic device to have a both low power consumption and a small propagation delay (fast switching speed), a low PDP is desirable. Power dissipation is proportional to the heat generated by the chip; Excessive heat dissipation may increase operating temperature and cause gate circuitry to drift out of its normal operating range; It will cause gates to generate improper output values. Thus, power dissipation of any gate implementation must be kept as low as possible. CMOS circuits dissipate power by charging and discharging the various load capacitances (mostly gate and wire capacitance, but also drain and some source capacitances) whenever they are switched. The charge moved is the capacitance multiplied by the voltage change. Multiply by the switching frequency to get the current used, and multiply by voltage again to get the characteristic switching power dissipated by a CMOS device: P = CV2f.

Noise Margin

Noise Margin is the difference between what the driver IC outputs as a valid logic voltage and what the receiver IC expects to see as a valid logic voltage. There are two different types of noise margin, one for a logic high value [1] and one for a logic low value [0]. The equations for noise margins are provided below.

Noise Margin Output high = V
OH [driving device] - VIH [receiving device]
Noise Margin Output low = VIL [receiving device] - VOL [driving device]

The higher the numbers the better, with negative numbers indicating in-operability.

Fan In

Fan-in is the number of inputs a gate has, like a two input AND gate has fan-in of two, a three input NAND gate as a fan-in of three. So a NOT gate always has a fan-in of one. The figure below shows the effect of fan-in on the delay offered by a gate for a CMOS based gate. Normally delay increases following a quadratic function of fan-in.

Fan Out

The number of gates that each gate can drive, while providing voltage levels in the guaranteed range, is called fan-out. The fan-out depends on the amount of electric current a gate can source or sink while driving other gates. The effects of loading a logic gate output with more than its rated fan-out has the following effects.
  • In the LOW state, the output voltage VOL may increase above VOLmax.
  • In the HIGH state, the output voltage VOH may decrease below VOHmin.
  • The operating temperature of the device may increase thereby reducing the reliability of the device and eventually causing the device failure
  • Output rise and fall times may increase beyond specifications
  • The propagation delay may rise above the specified value

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