Low power design

In today's chip industry, power consumption is the primary concern of the hardware designers who implement wireless and mobile applications. Though, EDA tools are emerging, many design decisions - which are influencing the power consumptions - are made at the system and architectural level prior to writing RTL. The power consumption of a circuit can be classified as either dynamic or static. Dynamic power consumption is a function of switched capacitance and supply voltages. Static power consumption comprises the circuit-activity-independent leakage power consumption. Leakage power depends on process technology parameters such as threshold voltages, supply voltages, circuit state, and temperature.

Methodology

Cells that do not perform a required function are turned off using sleep transistors. But instead of disabling just the clock signal, sleep transistors also disconnect cells from their power supply. Therefore, power gating reduces both dynamic and static power consumption. Power gating can be implemented in two different ways: fine or coarse grain.

FINE GRAIN power gating requires that each cell come with its own sleep transistor.

Advantage

• Good timing control

Disadvantages

• Increased area overhead
• Less leakage control
• Required a standard cell library with sleep transistor

COARSE-GRAIN power gating methodology is implemented using special sleep transistor cells. One sleep transistor cell is used to turn on and off a set of standard cells. The coarse-grained approach requires less area than fine-grain power gating due to the lower number of sleep transistors and less routing of enable signals for power gating. Fewer sleep transistors result in better leakage control.

Unlike fine grained power gating, when the power is switched off in coarse grain power gating, the power is disconnected from all the registers resulting in loss of data. If the data is to be preserved when the power is disconnected, then we need to store the data somewhere, where there is no power gating - This is done by a special register called "Retention" register. The key advantage of retention register is that they are simple to use and are very quick to save and restore the state.

State Retention Power Gating

This technique allows the voltage supply is reduced to zero for the majority of the SOC block's logic gates while maintaining the voltage supply for the state element of that block. The state of the SOC is always saved in the sequential components. Using the SRPG technique, when in the inactive mode, power to the combination logic is turned off and the sequential stays on thereby reducing the power consumption greatly when the application is in stop mode.

Gray Code Counter Implementation

A Gray code is an encoding of numbers so that adjacent numbers have a single digit differing by 1. The term Gray code is often used to refer to a Binary Reflected Gray Code. We can implement a gray code counter in a different ways. Consider the following table carefully.

B : 000, 001, 010, 011, 100, 101, 110, 111
G: 000, 001, 011, 010, 110, 111, 101, 100

To convert a binary number d1,d2,..,d(n-1),dn to its corresponding Binary Reflected Gray Code, start at the right with the digit dn (the LSB). If the d(n-1) is 1, replace dn by (1-dn); otherwise, leave it unchanged. Then proceed to d(n-1). Continue up to the first d1, which is kept the same. The resulting number g1,g2,..,g(n-1),gn is the Reflected Binary Gray Code.

The most common Gray code is where the lower half of the sequence is exactly the mirror image of first half with only the MSB inverted. We illustrate the 3-bit binary Gray code as an example.

Binary to gray code can be achieved by

gray[2] = binary[2];

gray[1] = binary[2] ^ binary[1];

gray[0] = binary[1] ^ binary[0];

A simple verilog code to implement this function is given by

assign gray = (binary>> 1) ^ binary; // Right shift by 1 and EX-OR with binary.

 module gray_cntr (  
     clock_in,
     rst_n,
     enable_in,
     cnt_out
    );
    
    // I/O Declarations

    input clock_in, rst_n, enable_in; 
    output [ 2:0] cnt_out;
    wire [2:0] cnt_out;
    reg [2:0] cnt;
    
    always @ (posedge clock_in or negedge rst_n) 
    if (!rst_n) 
      cnt <= 1'b0; 
    else if (enable_in) 
      cnt <= cnt + 1'b1; 
      
    assign cnt_out = { cnt[2], (^cnt[2:1]), (^cnt[1:0]) };
      
  endmodule

Mixed Signal Modeling

Designers today find themselves adding more and more analog and mixed-signal content to their creations. In the past, designers used different verification methodologies to verify designs that contains analog circuits. At the very highest levels of abstraction, system designers used Matlab to model systems that would be implemented with analog circuits; Designers now started using Verilog AMS ( Analog Mixed Signal ) - which allows the designer to model the analog circuit with different level of abstractions. The AMS extensions to Verilog is a good idea, particularly for SOC design. But so far they have received limited use, because they are relatively new and require learning new syntax and semantics and the acquisition of new simulation tools.

Here are some of the simple examples that shows how to write the behavioral model for analog circuits.

RESISTORS

One of the simplest models that can be described by Verilog-A is a resistor. In general, a resistor is a relationship between voltage and current, as in f(V, I) = 0 where V represents the voltage across the resistor, I represents the current through the resistor, and f is an arbitrary function of two arguments.

The equation for a simple linear resistor is V = IR where R is the resistance.

`include “disciplines.vams”

It defines the names electrical, V, and I, which are used in the model. It also defines other disciplines and natures.

module res(p,n);
inout p,n; // Positive and Negative terminals
electrical p,n;

The p and n ports are defined to be electrical, meaning the signals associated with the ports are expected to be voltage and current.

 parameter real r=0 from [0:inf]; // R value is from 0 to infinity

 analog
    V(p,n) <+ r*I(p,n);

The analog keyword introduces an analog process. An analog process is used to describe continuous time behavior. Syntactically, it is the analog keyword followed by a statement that describes the relationship between signals. This relationship must be true at all times.

endmodule

TRIANGLE WAVE FORM GENERATION

module V_triangle_generator(out);
 output out;
 voltage out;

 parameter real period = 10n from [0:inf],
                ampl   = 1;

 integer slope;
 real offset;

 analog
 begin
   @(timer(0,period))
   begin
     slope = +1;
     offset = $realtime;
     discontinuity(1);
   end

   @(timer(period/2,period))
   begin
     slope = -1;
     offset = $realtime;
     discontinuity(1);
   end

   V(out) <+ ampl * slope * (4*($realtime-offset)/period - 1);
 end
endmodule

Note that you can't compile this code in modelsim simulator tool. Synopsys' Discovery AMS, a mixed-signal simulator, allows designers to create entire designs with Accellera's Verilog-AMS language, launch all simulations from a single integrated control environment, and efficiently use parasitic data for post-layout analysis.

Verilog-AMS, a language standard approved by the Accellera EDA standards body, describes the behavior of analog and mixed-signal designs. The language is made up of three key parts: Verilog-D for digital designs, Verilog-A for analog, and mixed-signal extensions to specify domain-shifting algorithms.

You can download the Verilog-AMS language reference manual from here.

Serial to Parallel Data Conversion

A serial to parallel data conversion requires n-bit shift register. Therefore, a serial-in/parallel-out shift register converts data from serial format to parallel format. If four data bits are shifted in by four clock pulses via a single wire at serial-in, the data becomes available simultaneously on the four outputs parallel_out[3] to parallel_out[0] after the fourth clock pulse.

A serial to parallel data conversion circuit is used for converting a serial word supplied by some domain "X" to a parallel word so as to allow for the processing of the parallel word by a processor. The "X" domain supplies to the interface circuit a 'ready' pulse signal. The interface circuit, in response to the 'ready' pulse signal, supplies an 'ack' pulse and a 'clock' signal to the "X", so as to allow the serial word from the "X" to be transferred to the interface circuit, which then converts the serial word to a parallel word. An enable pulse signal supplied to the interface circuit effects the transfer of the parallel word from the interface circuit to the processor.

module serial_2_parallel (
clk_in,
rst_n,
ready_in,
shift_enable,
serial_in,
ack_out,
parallel_out );

// I/O declarations

input clk_in;
input rst_n;
input ready_in;
input shift_enable;
input serial_in;

output [3:0] parallel_out;
reg [3:0] parallel_out;
output ack_out;
reg ack_out;

wire [3:0] parallel_wire;

// A 4-bit shift register to convert serial to parallel

always@(posedge clk_in or negedge rst_n)
begin
if(rst_n == 1'b0)
begin
parallel_out <= 4'b0;
ack_out <= 1'b0; // ack_out is initially 0
end
// Shift enable is driven from tb as 1 when ack_out is 1
else if (shift_enable == 1'b1 && ready_in == 1'b1)
parallel_out <= ({serial_in, parallel_wire[3:1]});
else
begin
parallel_out <= parallel_wire;
ack_out <= 1'b1;
end
end

// Declare a 4-bit wire

assign parallel_wire = parallel_out;

endmodule

Coverage driven Random Verification

Coverage-driven random verification methods are becoming recognized as one of the best ways to verify complex IC designs. Cadence Design Systems, announced that new technologies have been integrated into the Cadence® Incisive® Enterprise verification family that enable engineering teams to address increasingly complex chip design. Incisive technologies now offer support for the newly developed Open Verification Methodology (OVM), a new aspect-oriented generation engine, and the second generation of Cadence transaction-based acceleration (TBA) with native support of multiple test-bench languages and numerous productivity enhancements.

To understand how to take advantage of this solution, cdn (cadence designer network) talked to Mr. Apurva Kalia, VP of R&D.

You can read his interview here.