ASIC Verification: Low power design

Thursday, July 24, 2008

Low power design

In today's chip industry, power consumption is the primary concern of the hardware designers who implement wireless and mobile applications. Though, EDA tools are emerging, many design decisions - which are influencing the power consumptions - are made at the system and architectural level prior to writing RTL. The power consumption of a circuit can be classified as either dynamic or static. Dynamic power consumption is a function of switched capacitance and supply voltages. Static power consumption comprises the circuit-activity-independent leakage power consumption. Leakage power depends on process technology parameters such as threshold voltages, supply voltages, circuit state, and temperature.


Cells that do not perform a required function are turned off using sleep transistors. But instead of disabling just the clock signal, sleep transistors also disconnect cells from their power supply. Therefore, power gating reduces both dynamic and static power consumption. Power gating can be implemented in two different ways: fine or coarse grain.

FINE GRAIN power gating requires that each cell come with its own sleep transistor.

  • Good timing control
  • Increased area overhead
  • Less leakage control
  • Required a standard cell library with sleep transistor
COARSE-GRAIN power gating methodology is implemented using special sleep transistor cells. One sleep transistor cell is used to turn on and off a set of standard cells. The coarse-grained approach requires less area than fine-grain power gating due to the lower number of sleep transistors and less routing of enable signals for power gating. Fewer sleep transistors result in better leakage control.

Unlike fine grained power gating, when the power is switched off in coarse grain power gating, the power is disconnected from all the registers resulting in loss of data. If the data is to be preserved when the power is disconnected, then we need to store the data somewhere, where there is no power gating - This is done by a special register called "Retention" register. The key advantage of retention register is that they are simple to use and are very quick to save and restore the state.

State Retention Power Gating

This technique allows the voltage supply is reduced to zero for the majority of the SOC block's logic gates while maintaining the voltage supply for the state element of that block. The state of the SOC is always saved in the sequential components. Using the SRPG technique, when in the inactive mode, power to the combination logic is turned off and the sequential stays on thereby reducing the power consumption greatly when the application is in stop mode.


Arun Kumar said...

good work ..

Suresh said...

Thanks Arun,

Keep reading!!!

Anonymous said...

Hi all. How are you?

Anonymous said...

Delete shis text plz. Sorry

Anonymous said...