ASIC Verification: Power consumption

Sunday, August 24, 2008

Power consumption

Here are some tips to predict the power consumption early in the design cycle i.e at the RTL Level.

Determine your design components power consumption

Find which components power consumption in your design is fixed by the specification and which components will be affected through power reduction techniques. For instance, input output power can be fixed at the specification level and memory power can also be fixed in the specification level. But memory can be powered down when not in use. If large amount of power is consumed by the clock in your design, then you need to have a clock gating techniques.

The designers can do an RTL power analysis before the design is synthesized. This analysis can't be as accurate as Gate level synthesis. But it gives an overall idea of potential power saving. For example, how much power could be saved if block "A" could be powered down 65 percent of the time, or if block "A" operated at 0.8 volt rather than 1 V?

Accurate switching activity from your simulation

To ensure an accurate power estimate, you need to use the most accurate data you have available at any given point in the design flow and revise your estimate as new data becomes available. But getting accurate switching activity is a huge challenge.

If switching activity data is not available from simulation, designers should estimate the switching activity on the chip's primary inputs and apply that estimate within the power analysis tool. Most power analysis tools can propagate the switching activity data through both the combinatorial and sequential logic.

No comments: