ASIC Verification: Mixed Signal Modeling

Saturday, July 19, 2008

Mixed Signal Modeling

Designers today find themselves adding more and more analog and mixed-signal content to their creations. In the past, designers used different verification methodologies to verify designs that contains analog circuits. At the very highest levels of abstraction, system designers used Matlab to model systems that would be implemented with analog circuits; Designers now started using Verilog AMS ( Analog Mixed Signal ) - which allows the designer to model the analog circuit with different level of abstractions. The AMS extensions to Verilog is a good idea, particularly for SOC design. But so far they have received limited use, because they are relatively new and require learning new syntax and semantics and the acquisition of new simulation tools.

Here are some of the simple examples that shows how to write the behavioral model for analog circuits.


One of the simplest models that can be described by Verilog-A is a resistor. In general, a resistor is a relationship between voltage and current, as in f(V, I) = 0 where V represents the voltage across the resistor, I represents the current through the resistor, and f is an arbitrary function of two arguments.

The equation for a simple linear resistor is V = IR where R is the resistance.

`include “disciplines.vams”

It defines the names electrical, V, and I, which are used in the model. It also defines other disciplines and natures.
module res(p,n);
inout p,n; // Positive and Negative terminals
electrical p,n;
The p and n ports are defined to be electrical, meaning the signals associated with the ports are expected to be voltage and current.

parameter real r=0 from [0:inf]; // R value is from 0 to infinity

V(p,n) <+ r*I(p,n);
The analog keyword introduces an analog process. An analog process is used to describe continuous time behavior. Syntactically, it is the analog keyword followed by a statement that describes the relationship between signals. This relationship must be true at all times.


module V_triangle_generator(out);
output out;
voltage out;

parameter real period = 10n from [0:inf],
ampl = 1;

integer slope;
real offset;

slope = +1;
offset = $realtime;

slope = -1;
offset = $realtime;

V(out) <+ ampl * slope * (4*($realtime-offset)/period - 1);

Note that you can't compile this code in modelsim simulator tool. Synopsys' Discovery AMS, a mixed-signal simulator, allows designers to create entire designs with Accellera's Verilog-AMS language, launch all simulations from a single integrated control environment, and efficiently use parasitic data for post-layout analysis.

Verilog-AMS, a language standard approved by the Accellera EDA standards body, describes the behavior of analog and mixed-signal designs. The language is made up of three key parts: Verilog-D for digital designs, Verilog-A for analog, and mixed-signal extensions to specify domain-shifting algorithms.

You can download the Verilog-AMS language reference manual from here.

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