ASIC Verification: What is Pipelining?

Tuesday, June 10, 2008

What is Pipelining?

Let me assume that I am going to build a car and I have all of the parts are lying around at my hand. Let us further assume that the main steps in the process are as follows:
  • Attach the wheel to the car,
  • Attach the engine,
  • Attach the seats,
  • Attach the body and
  • Paint everything.
Now let us assume that I require a specialist to perform each of these tasks. My Five friends are playing cricket. My first friend comes and attaches a wheel and goes back to play cricket. Assume that he takes 10 minutes. On his return, My second friend comes and attaches the engine and goes back once his job is done and so on. Once the first car has been completed, they start all over again. Obviously, this is very in-efficient scenarios as the whole process takes 50 minutes. Furthermore, for each of those 10 minutes, only one man is working. It would be much more efficient to have 5 cars in the same place. In this case, as soon as my first friend completed his work, he can go to the second car to attach a wheel while the second friend attaches the engine in first car. In this scenario, everyone will be working at all time.


Let us assume that we have a design that can be implemented as a series of blocks of combinational logics. Let's assume that we have a chunk of 3 combinational blocks. Let us say each block takes "t" nanoseconds to perform its task. In this case, it will take "3t" nanoseconds for a word of data to propagate through the function, starting with its arrival at the inputs to the first block and ends with its departure at the output pin of 3rd block.

We wouldn't want to present a new data to the inputs until we have stored the output results associated with the first word of data. The answer is to use a pipelined design technique in which the block of combinational logic are sandwiched b/w block of registers.

All of the register banks are driven by a common clock. On each active clock edge, the registers feeding a block of logic are loaded with the result from the previous stage. These values then propagate through that block of logic until they arrive at its outputs, at which point they are read to be loaded to the next set of register on the next clock. In this case, as soon as the pipeline is fully loaded, a new word of data can be processed every "t" nanoseconds.


Anonymous said...

one of the best explanation !!!!!gr8 job.

Anonymous said...

amazing explanation!!!