ASIC Verification: RTL Design techniques - Coding style

Monday, June 16, 2008

RTL Design techniques - Coding style

My focus has always been on what i’s good for synthesis with little regard to the effect on simulation speed.

Create a block level diagram before begin your coding
Draw a simple block diagrams of the functions of your design. This will also helpful in documentation. Use these block diagrams while code your design.

Always think of a fresher who read your RTL
Start with the inputs to your design - on the left side of block diagram - and describe the design’'s functionality from inputs to outputs. Don'’t try to be an ultra-efficient RTL coder. Please don’t forget to put comments. Have a comment “header” for each module, comment the functionality of each I/O, and use comments throughout the design to explain the “tricky” parts.

At the top level of your chip there should be 4 or 5 blocks: I/O pads, clock generator, reset circuit, and the core design. They are in separate blocks, because they might not be all synthesizable. Isolating them simplifies synthesis. Typically, the core design is hierarchical and organized by function.

Use separate always@ blocks for sequential logic and combinatorial logic
  1. It helps organize your RTL description
  2. There is a sequential optimization process in DC, which uses your coding style description of the sequential element to map it to the best sequential element in your technology library. When you combine sequential and combinatorial logic descriptions together, the tool can get confused and might not recognize the type of sequential element you are describing.
Use blocking for combinational and non-blocking for sequential
There is one good paper by Stuart Sutherland about the blocking and non-blocking assignments. This paper can be downloaded from here.

Know whether you have prioritized or parallel conditions
If the conditions are mutually exclusive, then a case statement is better, because it is easier to read and it organizes the parallel states of the description. If multiple conditions can occur at the same time, use the “if” statement and prioritize the conditions using “else if” for each subsequent condition.

Completely specify all branches of all conditional statements
If you completely specify all possible combinations of ones and zero’s for the different cases and you use the same select operator for all cases – DC will automatically recognize that case statement is fully specified and parallel.

Initialize output of conditional statements prior to defining the statements
Be careful selecting what value you initialize the output to. If there is'’t a default state for that part of the design – then try to pick the “most popular” state to initialize the output to – that should help reduce extra switching (power) during operation.

Use high level constructs (case, if, always@) as much as possible
Synthesis works best with high level RTL constructs. Low level gates or Boolean level constructs (verilog primitives) constrain DC.

Using good coding style and writing “safe” RTL code is not enough! Understand what you are implying and figure out in advance where are the potential problems. You should be able to manually synthesize in your head what you have described in your RTL description.


Pooja said...

hi plz tell me some rtl coding style to convert parallel data to serial and clock division

Suresh said...

Hi Pooja,

I'll try to put some coding technique on Parallel to serial data conversion. Meantime, You can have a look at the following page for the clock divider.

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siva said...

in my rtl design to have delay I need 4ns clock but at system level 2 clocks 250KH, 1MH are available.

How I can get 4ns clk (delay).

Is there any procedure to generate clk.

It should be synthesized.
plz suggest me some solution

Thank u.........

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