Re-timing is based on the concept of balancing out the positive and negative slacks throughout the design. In this context, the positive slack means, the amount of time by which the conditions are met and negative slack means, the amount of time by which the condition is not met.

For example, let us assume a pipe-lined design, whose frequency is such that the maximum register to register delay is 15ps. Now, let us assume that we have a situation as shown in Figure.

The longest timing path in the first block of combinational logic is 10ps - positive slack of 5ps.

The longest timing path in the second block of combination logic is 20ps - negative slack of 5ps. Once the initial path timing is calculated, combinational logic is moved across the register boundaries to steal from paths with a negative slack to donate to the paths with a postive slack.

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