ASIC Verification: VLSI FAQ

Tuesday, May 13, 2008

VLSI FAQ

Hi All,
I am back with bank after my UCSD mid-term test. Today I am going to post some of the important verilog questions.

How to solve setup & Hold violations in the design?

To solve setup violation
  • Optimizing / Restructuring Combinational logic between FFs.
  • Tweak flops to offer lesser setup delay.
  • Tweak launch-flop to have better slew at the clock pin, this will make CK->Q of launch flop to be fast there by helping fixing setup violations.
  • Play with skew (Tweak clock network delay, slow-down clock to capturing flop and fasten the clock to launch-flop) (otherwise called as Useful-skews)
To solve Hold Violations
  • Adding delay / buffer [as buffer offers lesser delay, we go for special Delay cells whose functionality Y=A, but with more delay]
  • Also, one can add lockup-latches [in cases where the hold time requirement is very huge, basically to avoid data slip]
What is tie-high and tie-low cells and where it is used?

Tie-high and Tie-Low cells are used to connect the Gate of the transistor to either Power or Ground. In deep sub micron process, if the Gate is connected to Power / Ground, the transistor might be turned ON / OFF due to power or ground bounce. The suggestion from foundry is to use Tie cells for this purpose. These cells are part of standard-cell library. The cells which require Vdd, comes and connect to Tie high.(so tie high is a power supply cell), while the cells which wants Vss connects itself to Tie-low.

What is metastability and steps to prevent it?

Metastability is an unknown state - it is neither Zero nor One. Metastability happens for the design systems violating setup or hold time requirements. Setup time is a requirement, that the data has to be stable before the clock-edge and hold time is a requirement, that the data has to be stable after the clock-edge. The potential violation of the setup and hold violation can happen when the data is purely asynchronous and clocked synchronously.

Steps to prevent Metastability:
  • Using proper synchronizers(two-stage or three stage), as soon as the data is coming from the asynchronous domain.
  • Using Faster flip-flops (which has narrower Metastable Window).
What is local-skew, global-skew,useful-skew mean?

Local skew : The difference between the clock reaching at the launching flop vs the clock reaching at the destination flip-flop of a timing-path.
Global skew : The difference between the earliest reaching flip-flop and latest reaching flip-flop for a same clock-domain.
Useful skew: Useful skew is a concept of delaying the capturing flip-flop clock path, this approach helps in meeting setup requirement within the launch and capture timing path. But the hold-requirement has to be met for the design.

What are the various timing-paths which i should take care in my STA runs?
  1. Timing path starting from an Input-port and ending at the Output port (purely combinational path).
  2. Timing path starting from an Input-port and ending at the Register.
  3. Timing path starting from an Register and ending at the Output-port.
  4. Timing path starting from an Register and ending at the Register.

What are the various Design constraints used while performing Synthesis for a design?
  1. Create the clocks ( Frequency, Duty-Cycle).
  2. Define transition-time requirements for the input-ports
  3. Specify load values for the output ports
  4. For the inputs and the outputs, specify the delay values (input delay and ouput delay), which are already consumed by the neighbour chip.
  5. Specify the case-setting (in case of a mux) to report the timing to a specific paths.
  6. Specify the False-paths in the design
  7. Specify the Multi-cycle paths in the design.
  8. Specify the clock-uncertainity values (with respect to jitter and the margin values for setup/hold).
  9. Specify few verilog constructs which are not supported by the synthesis tool.
What is meant by wire-load model?

In the synthesis tool, in order to model the wires we use a concept called Wireload models. Wireload models are statistical based on models with respect to Fanout. Say, for a particular technology based on our previous chip experience we have a rough estimate we know if a wire goes for "n" number of fanout, then we estimate its delay as say "x" delay units. So a model file is created with the fanout numbers and corresponding estimated delay values. This file is used while performing Synthesis to estimate the delay for Wires and to estimate the delay for cells.

What are the measures or precautions to be taken in the Design when the chip has both analog and digital portions?

As today's IC has analog components also inbuilt, some design practices are required for optimal integration. Ensure in the floor-planning stage that the analog block and the digital block are not siting close-by, to reduce the noise. Ensure that there exists separate ground for digital and analog ground to reduce the noise. Place appropriate guard-rings around the analog-macro's. Incorporating in-built DAC-ADC converters, allows us to test the analog portion using digital testers in an analog loop-back fashion. Perform techniques like clock-dithering for the digital portion.

What is meant by inferring latches, how to avoid it?

Consider the following :

always @(s1 or s0 or i0 or i1 or i2 or i3)
case ({s1, s0})
2'd0 : out = i0;

2'd1 : out = i1;
2'd2 : out = i2;
endcase

In a case statement if all the possible combinations are not compared and default is also not specified like in example above, a latch will be inferred. In above case if {s1,s0} =3, the previous stored value is reproduced. The same may be observed in IF statement in case an ELSE IF is not specified. To avoid inferring latches make sure that all the cases are mentioned if not default condition is provided.

Tell me structure of Verilog code you follow?

A good template for your Verilog file is shown below.

// Timescale directive tells the Simulator the Base units and Precision time unit of the simulation
`timescale 1 ns / 10 ps
module name (input and outputs);
// Parameter Declarations
parameter parameter_name = parameter value;
// Input / Output Declarations
input in1;
input in2; // Single bit Inputs
output [msb:lsb] out; // A Bus Output
// Internal signal register type declaration -
// Register types (only assigned within always statements).
reg register variable 1;

reg [msb:lsb] register variable 2;
// Internal signal. net type declaration - (only assigned outside always statements)
wire net variable 1;

// Hierarchy - Instantiating another module

reference name instance name (
.pin1 (net1),
.pin2 (net2),
.
.pinn (netn)
);

// Synchronous Procedures

always @ (posedge clock)
begin
.
end

// Combinatinal Procedures

always @ (signal1 or signal2 or signal3)
begin
.
end

assign net variable = combinational logic;


endmodule


3 comments:

Kundu said...

Excellent work .. i got few answers which I was searching for !!

arun said...

nice work, thanks alot.
can you tell about bonus cells, filler cells, dummy cells, procmon(process monitor) cells, constant cells...

Ankit said...

very helpful.....