To Maximize the Fault Coverage

The scan design technique depends on the controllability and observability of the state of DUT. Observe the following guidelines to maximize the fault coverage.

• Use Full Scan
  

• Use cells that have full functional models
  

• Fix all design rule violations, in particular
  

• Be careful when you use the gated clocks. If the clock signal at a FF is gated, a primary clock might not be able to control its state. If your design has clock gating, disable it in test mode.
  

• Generate the clocks off chip. If clock signals are generated on chip (Clock dividers), you can't control the state.
  

• Minimize the combinational feedback loops. CFL are difficult to test because they are hard to place in a known state.
  

• Use scan compatible sequential elements.
  

• Avoid uncontrollable asynchronous behavior.
  

• Control bi-directional from Primary Inputs.