Dividing a clock by an even number always generates 50% duty cycle output. Sometimes it is necessary to generate a 50% duty cycle frequency even when the input clock is divided by an odd or non-integer number. In this post I am going to talk about how to divide a clock by an odd number.

The easiest way to create an odd divider with a 50% duty cycle is to generate two clocks at half the desired output frequency with a quadrature-phase relationship (constant 90° phase difference between the two clocks). You can then generate the output frequency by exclusive-ORing the two waveforms together. Because of the constant 90° phase offset, only one transition occurs at a time on the input of the exclusive-OR gate, effectively eliminating any glitches on the output waveform.

Let’s see how it works by taking an example where the REF_CLK is divided by 3.

- Create a counter which is incremented on every rising edge of the input clock (REF_CLK) and the counter is reset to ZERO when the terminal count of counter reaches to (N-1). where N is odd number (3, 5, 7 and so on)

- Take two toggle flip-flops and generate their enables as follows; T-FF1 is enabled when the counter reaches '0' and T-FF2 is enabled when the counter reaches (N/2)+1.

- Output of T-FF1 is triggered on rising edge of REF_CLK and output of T-FF2 is triggered on the falling edge of REF_CLK.

- The divide by N clock is derived by simply Ex-ORing both the output of T-FFs.

## 7 comments:

Hi, It is really a nice approach. Keep it up.

Thats Really nice. What program do you use to create the timing diagram?

Can you explain for even number

The paper here presents an interesting solution for odd number dividers with 50% duty cycle -

www.onsemi.com/pub_link/Collateral/AND8001-D.PDF

How do you generate a 25% duty cycle instead of 50%?

hmmmm great .... really lovely .

you have explain concept of clock dividing very nicely

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