The solution for the problem is given here.
Monday, April 21, 2008
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Hello Everyone, This is My first blog ever. I have created this blog to discuss about various topics in the field of ASIC. You'll find lot of useful information about verification. Keep visiting this site for more updates.
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3 comments:
Hey man, why do you need that much big state-machine yaar..
latch 3 inputs like a shift register and write a combo logic that detects only two 1's in the Q outputs of shift register flops. that looks like
Y= Q0BAR . Q1 . Q2 + Q0 . Q1BAR . Q2 + Q0 . Q1BAR . Q2
This is as simple implementation as possible.
Correction,
Y= Q0BAR . Q1 . Q2 + Q0 . Q1BAR . Q2 + Q0 . Q1 . Q2BAR
Thanks Sai.
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