ASIC Verification: DAG

Thursday, April 17, 2008


Suppose we wanted to add an OAI gate, OAI(A, B,C) = not [(A + B) ⋅C], to the target gate library for our synthesizer. If the synthesizer uses the Directed Acyclic Graph (DAG) covering method for mapping equations to gates, what would be the appropriate primitive DAG (i.e., an equivalent circuit which uses only inverters and 2-input NANDs) for this new gate?

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