ASIC Verification: Sequence Detector - Solution

Monday, April 21, 2008

Sequence Detector - Solution



The solution for the problem is given here.

3 comments:

Sai said...

Hey man, why do you need that much big state-machine yaar..
latch 3 inputs like a shift register and write a combo logic that detects only two 1's in the Q outputs of shift register flops. that looks like
Y= Q0BAR . Q1 . Q2 + Q0 . Q1BAR . Q2 + Q0 . Q1BAR . Q2
This is as simple implementation as possible.

Sai said...

Correction,
Y= Q0BAR . Q1 . Q2 + Q0 . Q1BAR . Q2 + Q0 . Q1 . Q2BAR

Suresh said...

Thanks Sai.