ASIC Verification: Using System Verilog for Functional Verification

Saturday, February 16, 2008

Using System Verilog for Functional Verification


New to SystemVerilog? Mentor Graphics' Tom Fitzpatrick presents some simple techniques that will get you started right now with System Verilog for functional verification.

http://www.eetimes.com/showArticle.jhtml;jsessionid=P5SZ1MPHAHIZYQSNDLPCKHSCJUNN2JVN?articleID=174900365

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