Recently when I was browsing, I found out one article that compares the setup time and hold time of a FF to one analogy.

If the train leaves at 8:00 and you live 20 minutes away from the station, when should you leave from your house????? At 7:40.... If you leave after 7:40, you will miss the train. If you leave before 7:40, you should have enough time to get into the station. (Setup time is 20 minutes!!!).

Your friend needs help boarding the train and the train allows only 5 minutes for boarding. How long should you stay after you have arrived? 8:05 at the earliest... Without your help for the full 5 minutes, your friend is not able to board and will miss the train. (Hold time is 5 minutes!!!)

Every FF has time regions around the active clock edge in which the input should not change.

If the input changes in these restricted regions, the output may be derived from either:

the old input, the new input or even half-way in between.

I hope you all know about the setup time and hold time. Now we will see the different types of delays associated with a sequential circuit.

Maximum logic propagation delays:

Consider a synchronous circuit made of FFs with logic in between them.First FF input and output are D1 & Q1. There is some logic b/w 2 FFs and the output of logic goes to input of 2nd FF. Second FF's input and output are D2 & Q2.

The Q1 signal takes tCHQV to get out of the left FF.

The propagation delay through the gate(s) is tPD.

The D2 signal must arrive at the right FF at least tSETUP before the second clock edge.

The signal must get from the first FF to the next, in one clock cycle, thus -

tCLOCK ≥ tCHQV + tPD + tSETUP

So the gate delay, tPD, could take up the rest of the clock cycle. we can modify the above equation in the following way.

tCLOCK = tCHQV + tPD(max) + tSETUP

Minimum logic propagation delay:

One can have a valid minimum gate propagation delay. For a long hold time, one FF can flip within the long hold time and send its new output to the next FF fast enough to flip it on the same clock edge. This is when tCHQV < tHOLD.

To avoid double flips:

To avoid double flips:

tHOLD ≤ tCHQV + tPD(min)

Maximum logic delays with Clock skew:

I've dedicated one topic for clock skew. Now I just define what is clock skew and the positive & negative skew.

Clock skew is when the clock edge does not reach all the FFs at the same time. Positive skew define skew as positive when the data and clock are delayed in the same direction. In most schematics the right FF will receive the delayed clock.

Clock skew is when the clock edge does not reach all the FFs at the same time. Positive skew define skew as positive when the data and clock are delayed in the same direction. In most schematics the right FF will receive the delayed clock.

Positive skew increases the time available to get to the right-hand FF. If there is a positive skew in the clock, there is more time to get to the right hand FF, and tPD(MAX) is increased by the amount of the skew.

tCLOCK + tSKEW = tCHQV + tPD(MAX) + tSETUP

Minimum logic delays with Clock skew:

The minimum logic delay tPD(MIN) is made worse (increased) by positive skew. With positive clock skew, the clock to the lower flip-flop is delayed. The chance of a D1 change going through both flip-flops in one cycle increases. The tSKEW acts like an increase in the hold time of the lower flip-flop.

Clock Skew Related to Signal Delay:

Most circuits do not have a simple structure where one flip-flop is the source and another is the destination. Here we relate clock skew in circuits where the data travels in more complex paths.

Finding Minimum and Maximum Propagation Delays Given Clock Skew

• A register here is a set of edge-triggered simultaneously clocked D flip-flops.

• Registers are connected to other registers by combinational logic.

• Let the clock skew between registers be known.

• We will find the fast bound tPD(MIN) and the slow bound tPD(MAX) on the logic paths between each register pair.

The specification of FFs: tCHQV = 1 ns max; tHOLD = 0 ns min; tSETUP = 3 ns max; tSKEW A-B = +2 ns; tCLOCK = 16ns.

tPD(MIN) = tHOLD + tSKEW - tCHQV = 0 + 2 - 1 = 1 ns;

tPD(MAX) = tCLOCK + tSKEW - tSETUP - tCHQV = 16 + 2 - 3 - 1 = 14ns

For no clock skew, the propagation delay bounds are

tPD(MIN) = -1 ns (effectively 0????)

tPD(MAX) = 12ns; See the values of tPD during the presence of skew and without skew.

Finding Minimum and Maximum Propagation Delays Given Clock Skew

• A register here is a set of edge-triggered simultaneously clocked D flip-flops.

• Registers are connected to other registers by combinational logic.

• Let the clock skew between registers be known.

• We will find the fast bound tPD(MIN) and the slow bound tPD(MAX) on the logic paths between each register pair.

The specification of FFs: tCHQV = 1 ns max; tHOLD = 0 ns min; tSETUP = 3 ns max; tSKEW A-B = +2 ns; tCLOCK = 16ns.

tPD(MIN) = tHOLD + tSKEW - tCHQV = 0 + 2 - 1 = 1 ns;

tPD(MAX) = tCLOCK + tSKEW - tSETUP - tCHQV = 16 + 2 - 3 - 1 = 14ns

For no clock skew, the propagation delay bounds are

tPD(MIN) = -1 ns (effectively 0????)

tPD(MAX) = 12ns; See the values of tPD during the presence of skew and without skew.

## 1 comment:

Hmm.. I've thought about this very much..... and I agree with you to some degree.

frokostordning

Post a Comment