ASIC Verification: Engineering Change Order (ECO)

Saturday, February 16, 2008

Engineering Change Order (ECO)

I wanted to know about the ECO and how the flow will be. Recently I had a great time to work on the ECO netlist. In chip design, ECO is the process of inserting a logic change directly into the netlist after it has already been processed by an automatic tool. Before the chip masks are made, ECOs are usually done to save time, by avoiding the need for full ASIC synthesis. EDA tools are often built with incremental modes of operation to facilitate this type of ECO.

    RTL bug fix

    Correct your bug in RTL, run simulations for the specific scenarios to see if the problem has been fixed and it didn’t destroy any correct behavior.

    Implement ECO in Synthesis netlist

    Using your spare cells (Spare cells are basically elements embedded in the design which are not driving anything) and/or rewiring, implement the bug fix directly in the synthesis verilog netlist. Remember you do not re-synthesize the entire design, you are patching it locally.

    Run equivalence check between synthesis and RTL

    Using formal verification tool, run an equivalence check to see if the code you corrected really translates to the netlist you patched. If the two designs are equivalent you are sure that your RTL simulations would also have the same result (logically speaking) as the synthesis netlist.

    Implement ECO in layout netlist

    You will now have to patch your layout netlist as well. Notice that this netlist is very different than the synthesis netlist. It usually has extra buffers inserted for edge shaping or hold violation correction or maybe even totally differently logically optimized.


4 comments:

Nilesh said...

Hi,
Good to see your blog on ECO.

It would be interesting to know what you think are worth-solving research problems in ECO domain...

I am in academia and doing some work on ECO, so I am curious to know what practical problems do ppl encounter with existing tools and if at all, any academic research is required in any particular direction..

Thanks,
Nil

Nandy said...

Netlist ECO is the one of the areas with least coverage from EDA vendors. Most users would like to have some tools like ECO Compiler which Synopsys has deprecated several years ago. The hard part remains in flow variation in back end implementation. I am developing a GUI tool GOF to easy the netlist tracing and modification. You can visit www.nandigits.com if you have interest.
Some of my customers expressed interest in a feature to automatically extract the change from the newly synthesized netlist and apply the incremental changes to the netlist under ECO.
This is just where ECO Compiler failed. It's really a challenge and worthy academic research. Let me know if you have interest to do some research in this area.

arun said...

Hi, Thanks alot for the blog on ECO.


can you please write on ASIC flow. I know the brief one. can you please write on detailed way.

Thanks in advance.

Ben said...

Indeed, most users would like to have some tools like ECO Compiler which Synopsys has deprecated several years ago.

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