ASIC Verification: Increase the operational speed of the circuit

Saturday, September 20, 2008

Increase the operational speed of the circuit

There are numerous design techniques exists to increase the speed of the digital circuit. These design techniques are implemented automatically during synthesis. It also involves the trade-off between the area and speed, means that you have to pay for more area in order to achieve a speed.
  1. Use And-Or-Invert or Or-And-Invert gates wherever possible, since they are economical particularly for both area and speed.
  2. Feed the late arriving signals in your design late into the combinatorial circuit to balance the total gate delay along each path of the combinatorial circuit. To know more about late arriving signals, please go thorough it here.
  3. Use a maximum of 2 inputs on all combinatorial circuits in your design. For example, you can use two numbers of 2 input NAND gates and a 2 input NOR gate instead of using a 4 input AND gate.
  4. The bottom line is, if a boolean function with more than 2 inputs are decomposed into several simple gates, which results in more gates for the same function; but the total delay is reduced. According to the gate delay model, an N-input AND gate contains a branch with N transistors in series, resulting in an increased internal resistance of N*delta. Furthermore, the parasitic capacitance is also increased; therefore the internal delay of an N input AND gate is N(square)*delta. So if the NAND gate with 6 inputs is not decomposed, the internal delay will be rougly 0.7 ns as opposed to 0.42 ns with decomposition.
  5. Use Johnson counters instead of binary counters.
  6. An n-stage johnson counter produces a set of outputs of length 2n, which can be decoded to give a count sequence. The advantage of using this counter is that, having no combinatorial logic between flip-flops, it can be run at the maximum speed permitted by setup and hold time constraints. The disadvantage of a johnson counter is that, for a required count of m, it requires m/2 flip-flops, rather than log2(m) as required by a synchronous binary counter.

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