tag:blogger.com,1999:blog-1436736254097809592.post4201045105628523633..comments2023-10-29T04:44:08.184-07:00Comments on ASIC Verification: Asynchronous and Synchronous ResetAnonymoushttp://www.blogger.com/profile/18115567044084336439noreply@blogger.comBlogger8125tag:blogger.com,1999:blog-1436736254097809592.post-7603306900905563142012-04-03T02:28:08.903-07:002012-04-03T02:28:08.903-07:00The sentence
"if the edge of the reset deasse...The sentence<br />"if the edge of the reset deassertion is too close to the clock edge and violate the reset recovery time, then the output of FF goes to metastable." could be rephrased to "...goes metastable if FF output should change".<br /><br />Then the last reset synchronizer should work despite my earlier concerns. The second FF has been reset to 0 and it loads 0 from D input when reset is deasserted. Then only the first one would go metastable but that is not a problem.Erkkanoreply@blogger.comtag:blogger.com,1999:blog-1436736254097809592.post-14909777380236880942012-04-03T02:10:47.405-07:002012-04-03T02:10:47.405-07:00I was wondering the last figure sync_deass_async_a...I was wondering the last figure sync_deass_async_ass.JPG<br /><br />Note that reset controller is totally asynchronous to the fast clock. Hence, it seems that either (or both) synchronizing flip-flops could go metasable if reset de-assertion violates the recovery constraint. <br /><br />In the other reset synchronizer only the first dff can go metastable and the second only very very rarely. So they would be the recommended way, if I understood correctly.Erkkanoreply@blogger.comtag:blogger.com,1999:blog-1436736254097809592.post-75324410607483051292011-02-08T04:08:43.435-08:002011-02-08T04:08:43.435-08:00Yea , its interesting , but here i have a question...Yea , its interesting , but here i have a question in verification point of view ,<br />suppose according to design spec. reset should be synchronous but designer wrongly implemented as asynchronous reset, so without reviewing the code how can the verification engineer can check this ?smubarakhttp://designlogics.webs.comnoreply@blogger.comtag:blogger.com,1999:blog-1436736254097809592.post-62188990774267177602010-10-22T17:51:54.999-07:002010-10-22T17:51:54.999-07:00There is no possibility of failure of de-assertion...There is no possibility of failure of de-assertion of reset if the clk is slow ?Muralikrishna Pattajehttps://www.blogger.com/profile/06206571605075056138noreply@blogger.comtag:blogger.com,1999:blog-1436736254097809592.post-66019522298744430382010-07-10T17:06:57.329-07:002010-07-10T17:06:57.329-07:00thanks a lot for this!
your blog seems very helpfu...thanks a lot for this!<br />your blog seems very helpful.vehofugipihttps://www.blogger.com/profile/16336875805235059112noreply@blogger.comtag:blogger.com,1999:blog-1436736254097809592.post-44808918466864453582010-02-11T06:02:52.381-08:002010-02-11T06:02:52.381-08:00excellent explanation for Recovery time. in the sa...excellent explanation for Recovery time. in the same way can you explain about Removal timeUnknownhttps://www.blogger.com/profile/15949710218224370384noreply@blogger.comtag:blogger.com,1999:blog-1436736254097809592.post-74765036958460248972009-07-06T08:32:29.786-07:002009-07-06T08:32:29.786-07:00good job !!good job !!Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-1436736254097809592.post-18666616290180304462008-10-21T02:51:00.000-07:002008-10-21T02:51:00.000-07:00I found the article interesting. I design for FPGA...I found the article interesting. I design for FPGAs, and I used to use synchronous reset. I think I'll start to use your recommended topology, since it doesn't use up more resources.<BR/><BR/>Thanks and bye!!axaxaxas_mlohttps://www.blogger.com/profile/13906975551301330984noreply@blogger.com