tag:blogger.com,1999:blog-1436736254097809592.post4956072577927420974..comments2023-10-29T04:44:08.184-07:00Comments on ASIC Verification: Depth of the Asynchronous FIFOAnonymoushttp://www.blogger.com/profile/18115567044084336439noreply@blogger.comBlogger12125tag:blogger.com,1999:blog-1436736254097809592.post-56394973519313830532012-12-03T12:50:31.384-08:002012-12-03T12:50:31.384-08:00it can never be <50 clk><50 writes><...it can never be <50 clk><50 writes><50 writes><50 clk><br />or <50 writes><50 clk><50 writes><50 clk> or anything like that there will be a gap between the two 100 clk bursts.<br /><br /><br /><50 clk><50 writes>..........<50 writes><50 clk>sachin singhnoreply@blogger.comtag:blogger.com,1999:blog-1436736254097809592.post-77579385533977802012012-12-03T12:45:42.681-08:002012-12-03T12:45:42.681-08:00gksumanth and moorthy
please understand that the d...gksumanth and moorthy<br />please understand that the data is coming in burst.<br />before getting the second packet of 50 words the whole read and write of fifo would be done and it might/might not be reset before arrival of second data packet .<br /><br />even if we take your case in which for the first data packet the 50 words are written in the last 50 clock cycles of the 100 clk burst and for the second data packet 50 words are written in the first 50 clk cycle of 100 clk burst, the fifo depth calculations holds true as between these two burst of 100 clock cycles there would be a time duration in which the fifo read would be completed.<br /><br />the whole concept of FIFO is built around the assumption that the data will come in burst. If the data comes as a stream (which is your case) no matter how much fifo depth you have it will always overflow or u will loose data.sachin singhnoreply@blogger.comtag:blogger.com,1999:blog-1436736254097809592.post-43814523413125767522012-05-01T10:39:21.680-07:002012-05-01T10:39:21.680-07:00Can you please explain how to calculate the depth ...Can you please explain how to calculate the depth of fifo when Read Freq > Write Freq.rajeshnoreply@blogger.comtag:blogger.com,1999:blog-1436736254097809592.post-14993735579719930012012-03-20T16:26:44.462-07:002012-03-20T16:26:44.462-07:00Anonymous has a good point here... even if we put ...Anonymous has a good point here... even if we put two 100 cycle blocks together, the maximum can only be 50 writes per 100 cycles. The write sequence cannot be worse than <50 writes><50 idle><50 writes><50 idle>. Two 50-cycle bursts cannot be right after each other, otherwise the spec would be for 100 writes in 100 cycles. Thus the correct FIFO depth is 25 (not including synchronizer latency).Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-1436736254097809592.post-34907668733070322922012-03-07T06:37:14.341-08:002012-03-07T06:37:14.341-08:00Sumanth is right.Sumanth is right.Vijaynoreply@blogger.comtag:blogger.com,1999:blog-1436736254097809592.post-39867739868622446182011-06-15T15:28:43.018-07:002011-06-15T15:28:43.018-07:00I would have to disagree with sumanth and moorthy ...I would have to disagree with sumanth and moorthy - having 100 writes in 100 cycles is not what the author has designed for - he says burst of 50 every 100 clocks - worst case all 50 are consecutive. If you have a requirement for 100 writes for 100 clocks then definitely the calculation will be different.Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-1436736254097809592.post-46859238224125673642011-04-26T20:43:55.227-07:002011-04-26T20:43:55.227-07:00I agree with what Sumanth says and his calculation...I agree with what Sumanth says and his calculation is correct. <br /><br />Total Depth of FIFO should be 50 instead of 25.Moorthynoreply@blogger.comtag:blogger.com,1999:blog-1436736254097809592.post-70919789403437931662010-10-19T07:41:18.795-07:002010-10-19T07:41:18.795-07:00Have you considered the fact that this might work ...Have you considered the fact that this might work another way? I am wondering if anyone else has come across something <br />similar in the past? Let me know your thoughts...Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-1436736254097809592.post-5909638852665221902010-09-07T04:51:47.883-07:002010-09-07T04:51:47.883-07:00Thanks for sharing this link, but unfortunately i...Thanks for sharing this link, but unfortunately it seems to be down... Does anybody have a mirror or another source? Please answer to my post if you do!<br /><br />I would appreciate if a staff member here at chipverification.blogspot.com could post it.<br /><br />Thanks,<br />AlexAnonymousnoreply@blogger.comtag:blogger.com,1999:blog-1436736254097809592.post-25345363577501036592010-07-08T02:28:09.795-07:002010-07-08T02:28:09.795-07:00I am afraid this is not the worst case for calcula...I am afraid this is not the worst case for calculating the FIFO depth (scenario 2). Take 200 write clock cycles. Each 100 cycles can have 50 writes (which only needs 50 write cycles). Now, in the first 100 cycles, the write side writes from 50-100 cycles, and in the second 100 cycles, it writes in 100-150 cycles, it will be 100 cycles of continuous writing from the write agent. Considering 100 cycle window, the read agent lags the write agent (at half its frequency) by 50 words. I feel the depth should be 50 and not 25. You can mail me @ gksumanth@gmail.com for more detailssumanthhttps://www.blogger.com/profile/08835687057925927812noreply@blogger.comtag:blogger.com,1999:blog-1436736254097809592.post-29450569686414685622009-05-29T05:46:52.823-07:002009-05-29T05:46:52.823-07:00hi, when we use pointers in FIFO , each pointer(re...hi, when we use pointers in FIFO , each pointer(read & write) has to cross the domains. that means, we need synchronizer over here. the no. of flops used for this, adds the delay to the FIFO. now, depending on that delayed pointer, we need to decide the FIFO depth. this delay is called Synchronizer latency.Mohd Rafeeq Ahmedhttps://www.blogger.com/profile/05766944311081730272noreply@blogger.comtag:blogger.com,1999:blog-1436736254097809592.post-79984343367959314652008-10-20T08:12:00.000-07:002008-10-20T08:12:00.000-07:00synchronizer latency?could you explain it clearly!...synchronizer latency?<BR/>could you explain it clearly!<BR/>thanx in advance!Anonymousnoreply@blogger.com