ASIC Verification: FSM Problem

Thursday, April 17, 2008

FSM Problem

Construct a synchronous moore state machine with two inputs, A and B, and two outputs, X and Y. The machine accepts data on two input lines synchronously with the clock. The output X is 1 if and only if the data on the two input lines have been identical (i.e. A and B are both 1, or A and B are both 0) for the last three or more consecutive clock cycles. Output Y is 1 if and only if the data on the two input lines have been complements of each other (i.e. A = 1 and B = 0, or A = 0 and B = 1) for the last three or more consecutive clock cycles.

2 comments:

Anonymous said...

could you please post the solution or any pointers if possible.
thanks.

bunnu_vizag said...

Simple, Just XOR the inputs ie. A and B and then obtain a value say x.
So this x can be used as an input to the state machine and rest all is plain. :)